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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13601-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90630A Series
MB90632A/634A/P634A
s DESCRIPTION
The MB90630A series are 16-bit microcontrollers designed for high speed real-time processing in consumer product applications such as controlling video cameras, VCRs, or copiers. The series uses the F2MC*-16L CPU. The chips incorporate an eight channels 10-bit A/D converter, two channels 8-bit D/A converter, UART two channels, two channels serial interface, 8/16-bit up/down counter, 16-bit I/O timer (two channels input capture, four channels output compare, and one channel 16-bit free-run timer). *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
F2MC-16L CPU * Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication), maximum multiplier = 4 * Instruction set optimized for controller applications Object code compatibility with F2MC-16(H) Wide range of data types (bit, byte, word, and long word) Improved instruction cycles provide increased speed Additional addressing modes: 23 modes High code efficiency Access mothods (bank access, linear pointer)
(Continued)
s PACKAGE
100-pin Plastic LQFP 100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90630A Series
(Continued) High precision operations are enhanced by use of a 32-bit accumulator Extended intelligent I/O service (access area extended to 64 KB) Maximum memory space: 16 MB
* Enhanced high level language (C) and multitasking support insturctions Use of a system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Improved execution speed: Four byte instruction queue * Powerful interrupt function * Automatic data transfer function that does not use insturction (IIOS) Internal peripherals * ROM: 32 Kbytes (MB90632A) 64 Kbytes (MB90634A) One-time PROM: 64 Kbytes (MB90P634A) * RAM: 1 Kbytes (MB90632A) 2 Kbytes (MB90634A) 3 Kbytes (MB90P634A) * General-purpose ports: 82 ports max. * 10-bit A/D converter (RC successive approximation): eight channels (10-bit resolution, conversion time = 5.2 s at 4 MHz with a x 4 multiplier) * 8-bit D/A converter two channels (8-bit resolution) * UART (can also be used as a serial port) two channels * I/O expansion serial interface two channels * 8/16-bit PPG (can be set to either 8-bit x two channels or 16-bit x one channel) one channel * 16-bit I/O timer one channel (two channels input capture, four channels output compare, and one channel free-run timer) * Clock output generator * Timebase counter/watchdog timer (18-bit) * Low-power consumption modes * The device types are classified by the initial value of the oscillation stabilization delay time. Oscillation stabilization delay time initial value = 2.05 ms: MB90630A series (MB90632A/634A/P634A) * Package: LQFP-100 (QFP-100 planned) * CMOS technology
2
MB90630A Series
s PRODUCT LINEUP
Part number Parameter Classification ROM size RAM size CPU functions MB90P634A OTPROM 64 Kbyte 3 Kbyte Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time 32 Kbyte 1 Kbyte MB90632A Mask ROM 64 Kbyte 2 Kbyte MB90634A
: 340 : 8/16 bits : 1/7 bytes : 1/4/8/16/32 bits : 62.5 ns/4 MHz (PLL multiplier = 4) : 1000 ns/16 MHz (minimum)
Ports
(
I/O ports (CMOS/TTL) : 82 ports Input pull-up resistors available : 24 ports Can be set as open-drain outputs : 8 ports FPT-100P-M05 FPT-100P-M06
)
Package A/D converter D/A converter UART
10-bit resolution, 5.2 s conversion time (at 4 MHz with a x4 multiplier) RC successive approximation, 8 channels (multiplexed inputs) 8-bit resolution R-2R type, 2 channels (independent) Full-duplex, double-buffered (8-bit), internal baud rate correction circuit that uses the operating clock NRZ-type transfer, supports MIDI frequencies, 2 channels 8-bit data register. LSB-first or MSB-first operation can be selected. The transfer shift clock can be input externally. The internal shift clock includes a built-in operating clock correction circuit. 1 channel Can operate as two independent channels in 8-bit mode. Can also be used as a single-channel 16-bit PPG. 1 channel 6 event inputs. Can operate as two independent 8-bit up/down counter channels. Can also be used as a single-channel 16-bit counter. Includes reload and compare functions. 1 channel Consists of 2 x input capture, 4 x output compare, and 1 x free-run timer. 1 channel Timebase timer/watchdog timer (18-bit) Includes sleep, stop, and hardware standby functions The initial value of the oscillation stabilization delay time is 64 ms. The oscillation stabilization delay time can also be set to 0 ms, 2.05 ms, 8.19 ms, or 64 ms (for an crystal oscillator). The MB90630A series are for FAR oscillators. 8 inputs External interrupt mode (Interrupts can be generated from four different types of request signal) Selectable multiplier: 1/2/3/4 (Set a multiplier that does not exceed the assured operation frequency range.)
VPP is shared with the MD2 pin (for EPROM programming)
Serial interface
8/16-bit PPG 8/16-bit up/down counter 16-bit I/O timer Timer functions Low-power consumption modes Oscillation stabilization delay time External interrupt
PLL function Other
--
--
3
MB90630A Series
s PIN ASSIGNMENT
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P21/A17 P20/A16 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS PA4 PA3/OUT3 PA2/OUT2
P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 P70/SIN3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RST PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/ZIN1 P94/BIN1 P93/AIN1/IRQ7 P92/ZIN0 P91/BIN0 P90/AIN0/IRQ6 P67/PPG11 P66/PPG10 P65/CKOT P64/PPG01 P63/PPG00 P62/SCK2 P61/SOT2 P60/SIN2 P87 P86 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2
4
P71/SOT3 P72/SCK3 DVRH DVSS P73/DAO0 P74/DAO1 AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 VSS P54/AN4 P55/AN5 P56/AN6 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 HST
(FPT-100P-M05)
MB90630A Series
(TOP VIEW)
DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 VSS P54/AN4 P55/AN5 P56/AN6 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 P70/SIN3 P71/SOT3 P72/SCK3 DVRH 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA4 PA3/OUT3 PA2/OUT2 RST PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/ZIN1 P94/BIN1 P93/AIN1/IRQ7 P92/ZIN0 P91/BIN0 P90/AIN0/IRQ6 P67/PPG11 P66/PPG10 P65/CKOT P64/PPG01 P63/PPG00 P62/SCK2 P61/SOT2 P60/SIN2 P87 P86 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 HST MD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS
(FPT-100P-M06)
5
MB90630A Series
s PIN DESCRIPTION
Pin no. LQFP* 80 81 50 75 83 to 90
1
QFP* 82 83 52 77
2
Pin name X0 X1 HST RST P00 to P07
Circuit type A A C B Oscillator pin Oscillator pin
Function
Hardware standby input pin Reset input pin
85 to 92
D General-purpose I/O ports (STBC) Pull-up resistors can be set (RD07 to RD00 = "1") using the pull-up resistor setting register (RDR0). The setting does not apply for ports set as outputs (D07 to D00 = "1": invalid at the output setting). In external bus mode, the pins function as the lower data I/O or lower address outputs (AD00 to AD07). D General-purpose I/O ports (STBC) Pull-up resistors can be set (RD17 to RD10 = "1") using the pull-up resistor setting register (RDR1). The setting does not apply for ports set as outputs (D17 to D10 = "1": invalid at the output setting). In 16-bit external bus mode, the pins function as the upper data I/O or middle address outputs (AD08 to AD15). H General-purpose I/O ports (STBC) In external bus mode, pins for which the corresponding bit in the HACR register is "0" function as the P20 to P27 pins. In external bus mode, pins for which the corresponding bit in the HACR register is "1" function as the upper address output pins (A16 to A23). H General-purpose I/O port (STBC) Functions as the ALE pin in external bus mode. Functions as the address latch enable signal. H General-purpose I/O port (STBC) Functions as the RD pin in external bus mode. Functions as the read strobe output (RD). H General-purpose I/O port (STBC) Functions as the WR pin in external bus mode if the WRE bit in the EPCR register is "1". Functions as the lower data write strobe output (WRL). H General-purpose I/O port (STBC) Functions as the WRH pin in 16-bit external bus mode if the WRE bit in the EPCR register is "1". Functions as the upper data write strobe output (WRH).
AD00 to AD07 91 to 98 93 to 100 P10 to P17
AD08 to AD15 99, 100, 1 to 6 1 to 8 P20 to P27
A16 to A23
7
9
P30 ALE
8
10
P31 RD
10
12
P32
WRL 11 13 P33
WRH STBC: Incorporates standby control *1: LQFP (FPT-100P-M05) *2: QFP (FPT-100P-M06)
(Continued)
6
MB90630A Series
Pin no. LQFP*1 12 QFP*2 14
Pin name P34
Circuit type
Function
H General-purpose I/O port (STBC) Functions as the HRQ pin in external bus mode if the HDE bit in the EPCR register is "1". Functions as the hold request input pin (HRQ). H General-purpose I/O port (STBC) Functions as the HAK pin in external bus mode if the HDE bit in the EPCR register is "1". Functions as the hold acknowledge output (HAK) pin. H General-purpose I/O port (STBC) Functions as the RDY pin in external bus mode if the RYE bit in the EPCR register is "1". Functions as the external ready input (RDY) pin. H General-purpose I/O port (STBC) Functions as the CLK pin in external bus mode if the CKE bit in the EPCR register is "1". Functions as the machine cycle clock output (CLK) pin. G General-purpose I/O port (STBC) When UART0 is operating, the data at the pin is used as the serial input (SIN0). Can be set as an open-drain output port (OD40 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D40 = "0": invalid at the input setting). Functions as the UART0 serial input (SIN0). F General-purpose I/O port (STBC) Functions as the SOT0 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD41 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D41 = "0": invalid at the input setting). Functions as the UART0 serial data output pin (SOT0). G General-purpose I/O port (STBC) When UART0 is operating in external shift clock mode, the data at the pin is used as the clock input (SCK0). Also, functions as the SCK0 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD42 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D42 = "0": invalid at the input setting). Functions as the UART0 serial clock I/O pin (SCK0).
HRQ 13 15 P35
HAK 14 16 P36
RDY 15 17 P37
CLK 16 18 P40
SIN0 17 19 P41
SOT0 18 20 P42
SCK0 STBC: Incorporates standby control *1: LQFP (FPT-100P-M05) *2: QFP (FPT-100P-M06)
(Continued)
7
MB90630A Series
Pin no. LQFP*1 19 QFP*2 21
Pin name P43
Circuit type
Function
G General-purpose I/O port (STBC) When I/O expansion serial is operating, the data at the pin is used as the serial input (SIN1). Can be set as an open-drain output port (OD43 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D43 = "0": invalid at the input setting). Functions as the serial input for I/O expansion serial data. F General-purpose I/O port (STBC) Functions as the SOT1 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD44 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D44 = "0": invalid at the input setting). Functions as the output pin (SOT1) for I/O expansion serial data. G General-purpose I/O port (STBC) When I/O expansion serial is operating in external shift clock mode, the data at the pin is used as the clock input (SCK1). Also, functions as the SCK1 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD45 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D45 = "0": invalid at the input setting). Functions as the I/O expansion serial clock I/O pin (SCK1). F General-purpose I/O port (STBC) Can be set as an open-drain output port (OD46 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D46 = "0": invalid at the input setting). Functions as the external trigger input pin for the A/D converter. F General-purpose I/O port (STBC) Can be set as an open-drain output port (OD47 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D47 = "0": invalid at the input setting). K General-purpose I/O ports (STBC) The pins are used as analog inputs (AN0 to AN7) when the A/D converter is operating. I General-purpose I/O port (STBC) Functions as the UART1 serial input (SIN3). H General-purpose I/O port (STBC) Functions as the UART1 serial data output pin (SOT3). I General-purpose I/O port (STBC) Functions as the UART1 serial clock I/O pin (SCK0).
SIN1 20 22 P44
SOT1 22 24 P45
SCK1 23 25 P46
ADTG 24 26 P47
36 to 39, 41 to 44 25 26 27
38 to 41, P50 to P57 43 to 46 AN0 to AN7 27 28 29 P70 SIN3 P71 SOT3 P72 SCK3
STBC: Incorporates standby control *1: LQFP (FPT-100P-M05) *2: QFP (FPT-100P-M06) 8
(Continued)
MB90630A Series
Pin no. LQFP*1 30 QFP*2 32
Pin name P73
Circuit type
Function
L General-purpose I/O port (STBC) Functions as a D/A output pin when DAE0 = "1" in the D/A control register (DACR). Functions as D/A output 0 when the D/A converter is operating. L General-purpose I/O port (STBC) Functions as a D/A output pin when DAE1 = "1" in the D/A control register (DACR). Functions as D/A output 1 when the D/A converter is operating. I I I I I I General-purpose I/O port Functions as external interrupt request I/O 0. General-purpose I/O port Functions as external interrupt request I/O 1. General-purpose I/O port Functions as external interrupt request I/O 2. General-purpose I/O port Functions as external interrupt request I/O 3. General-purpose I/O port Functions as external interrupt request I/O 4. General-purpose I/O port Functions as external interrupt request I/O 5. H General-purpose I/O port (STBC) This applies in all cases. H General-purpose I/O port (STBC) This applies in all cases. E General-purpose I/O port (STBC) A pull-up resistor can be set (RD60 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D60 = "1": invalid at the output setting). Functions as a data input pin (SIN2) for I/O expansion serial. D General-purpose I/O port (STBC) Functions as the SOT2 pin if the SOE bit in the UMC register is "1". A pull-up resistor can be set (RD61 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D61 = "1": invalid at the output setting). Functions as an output pin (SOT2) for I/O expansion serial data.
DAO0 31 33 P74
DAO1 45 46 51 52 53 54 55 56 57 47 48 53 54 55 56 57 58 59 P80 IRQ0 P81 IRQ1 P82 IRQ2 P83 IRQ3 P84 IRQ4 P85 IRQ5 P86 P87 P60
SIN2 58 60 P61
SOT2 STBC: Incorporates standby control *1: LQFP (FPT-100P-M05) *2: QFP (FPT-100P-M06)
(Continued)
9
MB90630A Series
Pin no. LQFP*1 59 QFP*2 61
Pin name P62
Circuit type
Function
E General-purpose I/O port (STBC) When I/O expansion serial is operating in external shift clock mode, the data at the pin is used as the clock input (SCK2). Also, functions as the SCK2 pin if the SOE bit in the UMC register is "1". A pull-up resistor can be set (RD62 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D62 = "1": invalid at the output setting). Functions as the I/O expansion serial clock I/O pin (SCK2). D General-purpose I/O port (STBC) A pull-up resistor can be set (RD63 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D63 = "1": invalid at the output setting). Functions as the PPG00 output when PPG output is enabled. D General-purpose I/O port (STBC) A pull-up resistor can be set (RD64 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D64 = "1": invalid at the output setting). Functions as the PPG01 output when PPG output is enabled. D General-purpose I/O port (STBC) A pull-up resistor can be set (RD65 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D65 = "1": invalid at the output setting). Functions as the CKOT output when CKOT is operating. D General-purpose I/O port (STBC) A pull-up resistor can be set (RD66 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D66 = "1": invalid at the output setting). Functions as the PPG10 output when PPG output is enabled. D General-purpose I/O port (STBC) A pull-up resistor can be set (RD67 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D67 = "1": invalid at the output setting). Functions as the PPG11 output when PPG output is enabled. I General-purpose I/O port Input to channel 0 of the 8/16-bit up/down timer. Functions as an interrupt request input. I General-purpose I/O port (STBC) Input to channel 0 of the 8/16-bit up/down timer.
SCK2 60 62 P63
PPG00 61 63 P64
PPG01 62 64 P65
CKOT 63 65 P66
PPG10 64 66 P67
PPG11 65 67 P90 AIN0 IRQ6 66 68 P91 BIN0 STBC: Incorporates standby control *1: LQFP (FPT-100P-M05) *2: QFP (FPT-100P-M06)
(Continued)
10
MB90630A Series
(Continued)
Pin no. LQFP*1 67 68 QFP*2 69 70 Pin name P92 ZIN0 P93 AIN1 IRQ7 69 70 71 72 73 74 76 77 78 32 35 33 34 28 29 47 to 49 21, 82 71 72 73 74 75 76 78 79 80 34 37 35 36 30 31 49 to 51 23, 84 P94 BIN1 P95 ZIN1 P96 IN0 P97 IN1 PA0 OUT0 PA1 OUT1 PA2 OUT2 PA3 OUT3 PA4 AVCC AVSS AVRH AVRL DVRH DVSS MD0 to MD2 VCC Circuit type Function
I General-purpose I/O port (STBC) Input to channel 0 of the 8/16-bit up/down timer. I General-purpose I/O port Input to channel 1 of the 8/16-bit up/down timer. Functions as an interrupt request input. I General-purpose I/O port (STBC) Input to channel 1 of the 8/16-bit up/down timer. I General-purpose I/O port (STBC) Input to channel 1 of the 8/16-bit up/down timer. I General-purpose I/O port (STBC) Trigger input for channel 0 of the input capture. I General-purpose I/O port (STBC) Trigger input for channel 1 of the input capture. H General-purpose I/O port (STBC) Event output for channel 0 of the output compare. H General-purpose I/O port (STBC) Event output for channel 1 of the output compare. H General-purpose I/O port (STBC) Event output for channel 2 of the output compare. H General-purpose I/O port (STBC) Event output for channel 3 of the output compare. H General-purpose I/O port (STBC) -- -- -- -- -- -- C -- -- A/D converter power supply pin A/D converter power supply pin A/D converter external reference power supply pin A/D converter external reference power supply pin D/A converter external reference power supply pin D/A converter power supply pin Operating mode selection pins. Connect directly to VCC or VSS. Power supply (5.0 V) input pin Power supply (0.0 V) input pin
9, 40, 79 11, 42, 81 VSS STBC: Incorporates standby control *1: LQFP (FPT-100P-M05) *2: QFP (FPT-100P-M06)
11
MB90630A Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * Oscillator feedback Registance 1 M (approx.)
X0
Standby control signal
B
HYS
* Hysteresis input with pull-up Registance 50 k (approx.)
C
HYS
* Hysteresis input port
D
CTL
* Incorporates pull-up resistor control (for input) Registance 50 k (approx.) * CMOS level I/O
CMOS
E
CTL
* Incorporates pull-up resistor control (for input) Registance 50 k (approx.) * CMOS level output * Hysteresis input
HYS
F
Open-drain control signal
* CMOS level I/O * Open-drain control signal
CMOS
(Continued)
12
MB90630A Series
(Continued)
Type G
Open-drain control signal
Circuit
Remarks * CMOS level output * Hysteresis input * Incorporates open-drain control
HYS
H
* CMOS level I/O
CMOS
I
* CMOS level output * Hysteresis input
HYS
K
* CMOS level I/O * Analog input
CMOS Analog input
L
* CMOS level I/O * Analog output * Shared with D/A outputs
D/A output CMOS
M
CTL
* Incorporates pull-up resistor control (for input) Registance 50 k (approx.) * CMOS level output * Hysteresis input
HYS
13
MB90630A Series
s HANDLING DEVICES
1. Preventing Latch-up
Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if the voltage applied between VCC and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an "L" level to the RST pin, ensure that the "L" level is applied for at least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Precautions when Using an External Clock
Drive the X0 pin only when using an external clock. * Using an external clock
MB90630A X0
X1
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always turn off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before turning off the digital power supply (VCC). When turning the power on or off, ensure that AVRH does not exceed AVCC. Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
7. Program Mode
All bits (64 K x 16 bits) in the MB90P634A are "1" on delivery from Fujitsu or after erasing. To write data, selectively program the desired bits to "0". The value "1" cannot be written electrically.
14
MB90630A Series
8. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
9. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
10. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of 2 momentary fluctuation such as when power is switched.
15
MB90630A Series
s PROGRAMMING THE EPROM IN THE MB90P634A
In EPROM mode, the MB90P634A function as MBM27C1000 equivalents. By using a dedicated adapter socket, the devices can be programmed using a standard EPROM programmer.
1. Pin Assignment in EPROM Mode
* Pins compatible with the MBM27C1000 MBM27C1000 Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 Pin name VPP OE A15 A12 A07 A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 GND VCC PGM NC A14 A13 A08 A09 A11 A16 A10 CE D07 Pin number 49 10 98 95 6 5 4 3 2 1 100 99 83 84 85 -- -- 11 -- 97 96 91 92 94 7 93 8 90 MB90P634A Pin name MD2 (VPP) P32 P17 P14 P27 P26 P25 P24 P23 P22 P21 P20 P00 P01 P02 -- -- P33 -- P16 P15 P10 P11 P13 P30 P12 P31 P07
(Continued)
16
MB90630A Series
(Continued)
MBM27C1000 Pin number 20 19 18 17 Pin name D06 D05 D04 D03 Pin number 89 88 87 86 MB90P634A Pin name P06 P05 P04 P03
* Power supply and GND connection pins Type Power supply (VCC)
Pin number 28 50 21, 82 9 34 35 40 29 75 79 12 13 14
Pin name DVRH HST VCC VSS AVRL AVSS VSS DVSS RST VSS P34 P35 P36
GND
17
MB90630A Series
* Pins other than MBM27C1000-compatible pins Pin number Pin name 47 48 80 81 15 16 to 20 22 to 24 25 to 27 30 31 36 to 39 41 to 44 45 46 51 to 56 57 to 64 65 to 72 73 74 76 77 78 MD0 MD1 X0 X1 P37 P40 to P44 P45 to P47 P70 to P72 P73 P74 P50 to P53 P54 to P57 P80 P81 P82 to P87 P60 to P67 P90 to P97 PA0 PA1 PA2 PA3 PA4
Treatment Pull-up (4.7 k) OPEN
Connect pull-up resistors of approximately 1 M to each pin
2. EPROM Programmer Socket Adapter
Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. ROM-100SQF-32DP-16L
MB90P634APFV SQFP-100
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106
18
MB90630A Series
3. Programming Procedure
(1) Set the EPROM programmer for a MBM27C1000. (2) Load the program data between 10000H and 1FFFFH in the EPROM programmer. In the MB90P634A, ROM addresses FFFFFFH to FF0000H in operating mode correspond to addresses 1FFFFH to 10000H in EPROM mode.
FFFFFF H
1FFFF H
FF0000 H
10000 H
Operating mode
EPROM mode
(3) Set the MB90P634A, in the adapter socket and connect the adapter socket to the EPROM programmer. Take care to correctly align the device with the adapter. (4) Perform programming. (5) If programming cannot be performed successfully, connect a 0.1 F or similar capacitor between VCC and GND and between VPP and GND. Note: As mask ROM products (MB90632A, 634A) do not support EPROM mode, data cannot be read using an EPROM programmer. Performing a blank check for other than the above addresses results in either nonEPROM addresses being read or the blank check being unable to be performed.
19
MB90630A Series
s BLOCK DIAGRAM
CPU F2MC-16L series core Interrupt controller RAM 2 8 + 8PPG 2 (Output switching) x 1 channel
X0, 1 RST HST
4
Clock control circuit
ROM
PPG00, 01 PPG10, 11 x2 AIN0, 1 BIN0, 1 ZIN0, 1
Communications prescaler 2 2 2 2 2 2 I/O expansion serial interface x 2 channels UART x 2 channels F2MC-16 bus
U/D counter 8 bits x 2 (16 bits x 1)
SIN0, 3 SOT0, 3 SCK0, 3
Prescaler 8 External interrupts 2 3
CKOT
SIN1, 2 SOT1, 2 SCK1, 2
IRQ0 to IRQ7
I/O timers AVCC 2 AVRH, AVRL AVSS ADTG 8 AN0 to AN7 DAO0, 1 DVRH DVSS 2 D/A converter (8 bits) x 2 channels 16-bit input capture x 2 channels A/D converter (10 bits) 16-bit output capture x 4 channels 16-bit free-run timer
IN0, 1 OUT1 to OUT3
I/O ports 8 P00 to P07 8 P10 to P17 8 P20 to P27 8 P30 to P37 8 P40 to P47 8 P50 to P57 8 P60 to P67 5 P70 to P74 8 P80 to P87 8 P90 to P97 5 PA0 to PA4
P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input) P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input) P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input) P40 to P47 (8 pins) : Incorporates an open-drain setting register
20
MB90630A Series
s F2MC-16L CPU PROGRAMMING MODEL
* Dedicated Registers
AH AL USP SSP PS PC USPCU SSPCU USPCL SSPCL DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Accumulator User stack pointer System stack pointer Processor status Program counter User stack upper register System stack upper register User stack lower register System stack lower register Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General-purpose Registers
Maximum 32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4 RL1
RW2 RW1 RL0 000180H + RP x 10H RW0 16 bit
* Processor Status (PS)
ILM RP - I S T N CCR Z V C
21
MB90630A Series
s MEMORY MAP
FFFFFF H
Single chip
Internal ROM/External bus
External ROM/External bus
ROM area Address 1#
ROM area
FF0000 H
010000 H ROM area (FF bank image) Address 2# ROM area (FF bank image)
004000 H 002000 H Address 3# 000380 H RAM 000180 H 000100 H 0000C0 H Peripherals 000000 H : Internal : External : No access Peripherals Peripherals Registers RAM Registers RAM Registers
Type MB90632A MB90634A MB90P634A
Address #1 FF8000H FF0000H FF0000H
Address #2 008000H 004000H 004000H
Address #3 000500H 000900H 000D00H
22
MB90630A Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0B to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 pin register Port 0 resistance register Port 1 resistance register Port 6 resistance register Analog input enable register Serial mode register 0 Serial control register 0 Serial input register/ Serial output register 0 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Register Access name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 RDR6 ADER SMR0 SCR0 SIDR/ SODR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART0 Resource Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 Port 0 Port 1 Port 6 Port 5, A/D Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ---XXXXX XXXXXXXX XXXXXXXX ---XXXXX 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 - -- 00 00 0 0 00 00 00 0 0 00 00 00 0 - -- 00 00 0 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 0 00 00 00 0 1 11 11 11 1 00000000 00000100 XXXXXXXX
Reserved area
(Continued)
23
MB90630A Series
Address 23H 24H 25H 26H 27H 28H 29H 2AH 2B to 2FH 30H 31H 32H 33H 34 to 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47 to 4FH 50H
Register Serial status register 0
Serial mode control status register 0 Serial mode control status register 0
Register Access name SSR0 SMCS0 SMCS0 SDR0 CDCR SMCS1 SMCS1 SDR1 ENIR EIRR ELVR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource UART0 I/O expansion serial interface 0 Communications prescaler I/O expansion serial interface 1
Initial value 0 00 01 -0 0 ----0000 00000010 XXXXXXXX 0---1111 ----0000 00000010 XXXXXXXX 00000000
Serial data register 0 Clock division control register
Serial mode control status register 1 Serial mode control status register 1
Serial data register 1 Interrupt/DTP enable register Interrupt/DTP source register Request level setting register
Reserved area XXXXXXXX 00000000 00000000 00000000 A/D converter R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit I/O timer output compare (channel 0 to 3) 8/16 bit PPG CKOT output D/A converter 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX -------0 -------0 -----000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0X000XX1 0X 0 0 0 0 0 1 0 00 00 00 0
DTP/External interrupts
Reserved area Control status register Data register D/A converter data register 0 D/A converter data register 1 D/A control register 0 D/A control register 1 Clock control register Reload register L (channel 0) Reload register H (channel 0) Reload register L (channel 1) Reload register H (channel 1)
PPG0 operation mode control register PPG1 operation mode control register
ADCS1 ADCS2 ADCR1 ADCR2 DAT0 DAT1 DACR0 DACR1 CLKR PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGOE
R/W
Reserved area
PPG0, 1 output control register
Reserved area Lower compare register channel 0 OCCP0 R/W XXXXXXXX
(Continued)
24
MB90630A Series
Address 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5C to 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69 to 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH
Register Upper compare register channel 0 Lower compare register channel 1 Upper compare register channel 1 Lower compare register channel 2 Upper compare register channel 2 Lower compare register channel 3 Upper compare register channel 3
Compare control status register channel 0 Compare control status register channel 1 Compare control status register channel 2 Compare control status register channel 3
Register Access name OCCP0 OCCP1 OCCP2 OCCP3 OCS0 OCS1 OCS2 OCS3 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W -- R/W R/W R/W
Resource
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ---00000 0000--00 ---00000 0000--00 XXXXXXXX XXXXXXXX
16-bit I/O timer Output compare (channel 0 to 3)
Reserved area
Lower input capture register channel 0 Upper input capture register channel 0 Lower input capture register channel 1 Upper input capture register channel 1
IPCP0 IPCP1 ICS -- TCDTL TCDTH TCCS UDCR0 UDCR1 RCR0 RCR1 CSR0 -- CCRL0 CCRH0 CSR1 -- CCRL1
16-bit I/O timer Input capture (channel 0, 1)
XXXXXXXX XXXXXXXX 0 00 00 00 0 -------- 00000000 00000000 0 00 00 00 0 00000000 0 00 00 00 0 00000000 0 00 00 00 0 0 00 00 00 0
Input capture control status register Reserved area Lower timer data register Upper timer data register Timer control status register Up/down count register channel 0 Up/down count register channel 1 Reload compare register channel 0 Reload compare register channel 1 Counter status register channel 0 Reserved area Counter control register channel 0 Counter status register channel 1 Reserved area Counter control register channel 1
16-bit I/O timer Free-run timer (channel 0, 1)
Reserved area R W R/W -- R/W R/W -- R/W 8/16-bit up/down timer/counter
-------- -0000000 00000000 0 00 00 00 0 -------- - 00 00 00 0
(Continued)
25
MB90630A Series
Address 7BH 7C to 87H 88H 89H 8AH 8BH 8C to 9EH 9FH A0H A1H A2 to A4H A5H A6H A7H A8H A9H AA to AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH
Register Counter control register channel 1 Serial mode register 1 Serial control register 1 Serial input register 1/serial output register 1 Serial status register 1 Delayed interrupt generation/ clear register Low-power consumption mode register Clock selection register Auto-ready function selection register External address output control register Bus control signal selection register Watchdog timer control register Timebase timer control register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13
Register name CCRH1
Access R/W
Resource 8/16-bit up/down timer/counter
Initial value -0000000
Reserved area SMR1 SCR1 SIDR1/ SODR1 SSR1 R/W R/W R/W R/W Delayed interrupt generation module Low-power consumption Low-power consumption UART1 00000000 00000100 XXXXXXXX 0 00 01 -0 0
Reserved area (Accessing 90H to 9EH is prohibited.) DIRR LPMCR CKSCR R/W R/W R/W -------0 0 00 11 00 0 1 10 01 10 0
Reserved area ARSR HACR ECSR WDTC TBTC ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller External pins External pins External pins Watchdog timer Timebase timer 0011--00 ----0000 00 0 0* 0 0- XXXXX111 1 -- 00 10 0 00000111 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1 0 00 00 11 1
Reserved area
(Continued)
26
MB90630A Series
(Continued)
Address BEH BFH C0 to FFH Register Interrupt control register 14 Interrupt control register 15 Reserved area Register name ICR14 ICR15 -- Access R/W R/W -- Resource Interrupt controller -- Initial value 00000111 00000111 --
Initial values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". * : The initial value of this bit is "0" or "1". X: The initial value of this bit is undefined. -: This bit is not used. The initial value is undefined. Note: Areas below address 0000FFH not listed in the table are reserved areas. These addresses are accessed by internal access. No access signals are output on the external bus.
27
MB90630A Series
s INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO INTERRUPT SOURCES
Interrupt source Reset INT 9 instruction Exception A/D converter DTP 0 (External interrupt 0)
16-bit free-run timer (I/O timer) overflow
I2OS support x x x
Interrupt vector Number #08 #09 #10 #11 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #28 #29 #30 #31 #32 #33 #34 #36 #37 #38 #39 #40 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
Interrupt control register ICR -- -- -- ICR00 ICR01 ICR02 ICR03 ICR04 Address -- -- -- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H
I/O expansion serial 1 DTP 1 (External interrupt 1) I/O expansion serial 2 DTP 2 (External interrupt 2) DTP 3 (External interrupt 3) 8/16-bit PPG 0 counter borrow 8/16-bit U/D counter 0 compare 8/16-bit U/D counter 0 underflow/ overflow, up/down invert 8/16-bit PPG 1 counter borrow DTP 4/5 (External interrupt 4/5)
Output compare (channel 2) match (I/O timer) Output compare (channel 3) match (I/O timer)
ICR05
0000B5H
ICR06 ICR07 ICR08 ICR09
0000B6H 0000B7H 0000B8H 0000B9H
DTP 6 (External interrupt 6) 8/16-bit U/D counter 1 compare 8/16-bit U/D counter 1 underflow/ overflow, up/down invert
Input capture (channel 0) read (I/O timer) Input capture (channel 1) read (I/O timer) Output compare (channel 0) match (I/O timer) Output compare (channel 1) match (I/O timer)
ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
DTP 7 (External interrupt 7) UART0 receive complete UART1 receive complete UART0 transmit complete UART1 transmit complete Reserved Delayed interrupt x x
#41 #42
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request). : Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (stop request present). : Indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: For resources in which two interrupt sources share the same interrupt number, the I2OS interrupt clear signal clears both interrupt request flags. 28
MB90630A Series
s PERIPHERAL RESOURCES
1. Parallel Ports
(1) I/O Ports Each port pin can be specified as either an input or output by its corresponding direction register when the pin is not set for use by a peripheral. When a port is set as an input, reading the data register always reads the value corresponding to the pin level. When a port is set as an output, reading the data register reads the data register latch value. The same applies when reading using a read-modify-write instruction. When used as control outputs, reading the data register reads the control output value, irrespective of the direction register value. Note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data register before switching a pin from input to output, the instruction reads the input level at the pin and not the data register latch value. * Block Diagram
Data register read Internal data bus Data register Data register write Direction register Direction register write Pin
Direction register read
29
MB90630A Series
(2) Register Configuration
bit Address: 000000H Address: 000001H Address: 000002H Address: 000003H Address: 000004H Address: 000005H Address: 000006H Address: 000007H Address: 000008H Address: 000009H Address: 00000AH bit Address: 000010H Address: 000011H Address: 000012H Address: 000013H Address: 000014H Address: 000015H Address: 000016H Address: 000017H Address: 000018H Address: 000019H Address: 00001AH
15/7 P07 P17 P27 P37 P47 P57 P67 -- P87 P97 -- 15/7 D07 D17 D27 D37 D47 D57 D67 -- D87 D97 -- 15
14/6 P06 P16 P26 P36 P46 P56 P66 -- P86 P96 -- 14/6 D06 D16 D26 D36 D46 D56 D66 -- D86 D96 -- 14
13/5 P05 P15 P25 P35 P45 P55 P65 -- P85 P95 -- 13/5 D05 D15 D25 D35 D45 D55 D65 -- D85 D95 -- 13
12/4 P04 P14 P24 P34 P44 P54 P64 P74 P84 P94 PA4 12/4 D04 D14 D24 D34 D44 D54 D64 D74 D84 D94 DA4 12
11/3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 PA3 11/3 D03 D13 D23 D33 D43 D53 D63 D73 D83 D93 DA3 11
10/2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 PA2 10/2 D02 D12 D22 D32 D42 D52 D62 D72 D82 D92 DA2 10
9/1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 PA1 9/1 D01 D11 D21 D31 D41 D51 D61 D71
8/0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 8/0 D00 D10 D20 D30 D40 D50 D60 D70 D80 Port 0 direction register (DDR0) Port 1 direction register (DDR1) Port 2 direction register (DDR2) Port 3 direction register (DDR3) Port 4 direction register (DDR4) Port 5 direction register (DDR5) Port 6 direction register (DDR6) Port 7 direction register (DDR7) Port 8 direction register (DDR8) Port 9 direction register (DDR9) Port A direction register (DDRA) Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 9 data register (PDR9) Port A data register (PDRA)
D81 D91 D90 DA1 DA0 9 8
bit Address: 00001BH
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
Port 4 pin register (ODR4)
bit Address: 00001CH Address: 00001DH Address: 00001EH
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60 15 14 13 12 11 10 9 8
Port 0 resistor register (RDR0) Port 1 resistor register (RDR1) Port 6 resistor register (RDR6)
bit Address: 00001FH
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Port 5 analog input enable register (ADER)
30
MB90630A Series
(3) Register Details * Port Data Registers
bit PDR0 Address: 000000H bit PDR1 Address: 000001H bit PDR2 Address: 000002H bit PDR3 Address: 000003H bit PDR4 Address: 000004H bit PDR5 Address: 000005H bit PDR6 Address: 000006H bit PDR7 Address: 000007H bit PDR8 Address: 000008H bit PDR9 Address: 000009H bit PDRA Address: 00000AH
7 P07
6 P06
5 P05
4 P04
3 P03
2 P02
1 P01
0 P00
Initial value Undefined
Access R/W*
15 P17 7 P27
14 P16 6 P26
13 P15 5 P25
12 P14 4 P24
11 P13 3 P23
10 P12 2 P22
9 P11 1 P21
8 P10 0 P20 Undefined R/W* Undefined R/W*
15 P37 7 P47 15 P57
14 P36 6 P46 14 P56
13 P35 5 P45 13 P55
12 P34 4 P44 12 P54
11 P33 3 P43 11 P53
10 P32 2 P42 10 P52
9 P31 1 P41 9 P51
8 P30 0 P40 8 P50 Undefined R/W* Undefined R/W* Undefined R/W*
7 P67 15 --
6 P66 14 --
5 P65 13 --
4 P64 12 P74
3 P63 11 P73
2 P62 10 P72
1 P61 9 P71
0 P60 8 P70 Undefined R/W* Undefined R/W*
7 P87 15 P97
6 P86 14 P96
5 P85 13 P95
4 P84 12 P94
3 P83 11 P93
2 P82 10 P92
1 P81 9 P91
0 P80 8 P90 Undefined R/W* Undefined R/W*
7 --
6 --
5 --
4 PA4
3 PA3
2 PA2
1 PA1
0 PA0 Undefined R/W*
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows. * Input mode Read: Reads the corresponding pin level. Write: Writes to the output latch. * Output mode Read: Reads the value of the data register latch. Write: The value is output from the corresponding pin.
31
MB90630A Series
* Port Direction Registers
bit DDR0 Address: 000010H bit DDR1 Address: 000011H bit DDR2 Address: 000012H bit DDR3 Address: 000013H bit DDR4 Address: 000014H bit DDR5 Address: 000015H bit DDR6 Address: 000016H bit DDR7 Address: 000017H bit DDR8 Address: 000018H bit DDR9 Address: 000019H bit DDRA Address: 00001AH
7 D07
6 D06
5 D05
4 D04
3 D03
2 D02
1 D01
0 D00
Initial value 00000000B
Access R/W
15 D17 7 D27
14 D16 6 D26
13 D15 5 D25
12 D14 4 D24
11 D13 3 D23
10 D12 2 D22
9 D11 1 D21
8 D10 0 D20 00000000B R/W 00000000B R/W
15 D37 7 D47 15 D57
14 D36 6 D46 14 D56
13 D35 5 D45 13 D55
12 D34 4 D44 12 D54
11 D33 3 D43 11 D53
10 D32 2 D42 10 D52
9 D31 1 D41 9 D51
8 D30 0 D40 8 D50 00000000B R/W 00000000B R/W 00000000B R/W
7 D67 15 --
6 D66 14 --
5 D65 13 --
4 D64 12 D74
3 D63 11 D73
2 D62 10 D72
1 D61 9 D71
0 D60 8 D70 -----000B R/W 00000000B R/W
7 D87 15 D97
6 D86 14 D96
5 D85 13 D95
4 D84 12 D94
3 D83 11 D93
2 D82 10 D92
1 D81 9 D91
0 D80 8 D90 00000000B R/W 00000000B R/W
7 --
6 --
5 --
4 DA4
3 DA3
2 DA2
1 DA1
0 DA0 ---00000B R/W
When pins are used as ports, the register bits control the corresponding pins as follows. 0: Input mode 1: Output mode Bits are set to "0" by a reset.
32
MB90630A Series
* Port Resistance Registers
bit RDR0 Address: 00001CH bit RDR1 Address: 00001DH bit RDR6 Address: 00001EH
7 RD07 15 RD17 7 RD67
6 RD06 14 RD16 6 RD66
5 RD05 13 RD15 5 RD65
4 RD04 12 RD14 4 RD64
3 RD03 11 RD13 3 RD63
2 RD02 10 RD12 2 RD62
1 RD01 9 RD11 1 RD61
0 RD00 8 RD10 0 RD60 00000000B 00000000B Initial value 00000000B
* Block Diagram
Pull-up resistor (approx. 50 k)
Internal data bus
Data register
Port I/O
Direction register
Resistance register
Notes: * Input resistance register R/W Controls the pull-up resistor in input mode. 0: Pull-up resistor disconnected in input mode. 1: Pull-up resistor connected in input mode. The setting has no meaning in output mode (pull-up resistor disconnected). The direction register (DDR) sets input or output mode. * The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance). * This function is disabled when using an external bus. In this case, do not write to this register.
33
MB90630A Series
* Port Pin Register
bit ODR4 Address: 00001BH 7 OD47 6 OD46 5 OD45 4 OD44 3 OD43 2 OD42 1 OD41 0 OD40 Initial value 00000000B
* Block Diagram
Internal data bus
Data register
Port I/O
Direction register
Pin register
Notes: * Pin register R/W Performs open-drain control in output mode. 0: Operate as a standard output port in output mode. 1: Operate as an open-drain output port in output mode. The setting has no meaning in input mode (output Hi-z). The direction register (DDR) sets input or output mode * The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance). * This function is disabled when using an external bus. In this case, do not write to this register. * Analog Input Enable Register
bit ADER Address: 00001FH
15 ADE7 (R/W)
14 ADE6 (R/W)
13 ADE5 (R/W)
12 ADE4 (R/W)
11 ADE3 (R/W)
10 ADE2 (R/W)
9 ADE1 (R/W)
8 ADE0 (R/W) Initial value 11111111B
Controls each port 5 pin as follows. 0: Port input mode 1: Analog input mode Set to "1" by a reset.
34
MB90630A Series
2. UART
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK synchronous communications. The UART has the following features. * Full duplex, double buffered * Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer * Supports multi-processor mode * Built-in dedicated baud rate generator Asynchronous: 9615, 31250, 4808, 2404, 1202 bps CLK synchronous: 1 Mbps, 500 Kbps, 250 Kbps, 125 Kbps, and 62.5 * * * * Supports flexible baud rate setting using an external clock Error detect function (parity, framing, and overrun) NRZ type transmission signal Intelligent I/O service support For a 6, 8, 10, 12, or 16 MHz clock.
(1) Register Configuration
15 CDCR SCR SSR 8 bits
8
7 -- SMR SIDR (R)/SODR (W) 8 bits
0 (R/W) (R/W) (R/W)
bit Address: 000020H 000088H bit Address: 000021H 000089H bit Address: 000022H 00008AH bit Address: 000023H 00008BH bit Address: 000027H
7 MD1 15 PEN 7 D7 15 PE 15 MD
6 MD0 14 P 6 D6 14 ORE 14 --
5 CS2 13 SBL 5 D5 13 FRE 13 --
4 CS1 12 CL 4 D4 12 RDRF 12 --
3 CS0 11 A/D 3 D3 11 TDRE 11 DIV3
2
Reserved
1 SCKE 9 RXE 1 D1 9 RIE 9 DIV1
0 SOE 8 TXE 0 D0 8 TIE 8 DIV0
Serial mode register 0, 1 (SMR0, 1) Serial control register 0, 1 (SCR0, 1) Serial input register/ Serial output register 0, 1 (SIDR/SODR0, 1) Serial status register 0, 1 (SSR0, 1) Clock division control register (CDCR)
10 REC 2 D2 10 -- 10 DIV2
35
MB90630A Series
(2) Block Diagram
Control signals
Reception interrupt (to CPU)
Dedicated baud rate generator Upper 8/16-bit PPG timer (Connected internally) Transmission clock pulses Clock select circuit Reception clock pulses
SCK0, 1 Transmission interrupt (to CPU)
External clock Reception control circuit SIN0, 1 Start bit counter Reception bit counter Reception parity counter Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter
SOT0, 1
Reception status detection circuit
Reception shifter
Transmission shifter
Reception error occurrence signal for I2OS (to CPU)
End of reception SIDR
Start of transmission SODR
F2MC-16 bus
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
36
MB90630A Series
3. I/O Expansion Serial Interface
This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSBfirst or MSB-first data transfer can be selected. The following two serial I/O operation modes are available. * Internal shift clock mode: Data transfer is synchronized with the internal clock. * External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By manipulating the general-purpose port that shares the external pin (SCK), this mode also enables the data transfer operation to be driven by CPU instructions. (1) Register Configuration
bit Address: 000025H 000029H bit Address: 000024H 000028H bit Address: 000026H 00002AH 15 14 13 SMD0 5 -- 5 D5 12 SIE 4 -- 4 D4 11 SIR 3 MODE 3 D3 10 BUSY 2 BDS 2 D2 9 STOP 1 SOE 1 D1 8 STRT 0 SCOE 0 D0 Serial mode control status registers 0, 1 (SMCS0, 1) Serial data registers 0, 1 (SDR0, 1)
SMD2 SMD1 7 -- 7 D7 6 -- 6 D6
(2) Register Details * Serial Mode Control Status Register (SMCS)
bit SMCS Address: 000025H 000029H bit SMCS Address: 000024H 000028H 15 14 13 SMD0 (R/W) 5 -- 12 SIE 11 SIR 10 BUSY (R) 2 BDS (R/W) 9 STOP 8 STRT Initial value 00000010B
SMD2 SMD1 (R/W) 7 -- (R/W) 6 --
(R/W) (R/W*1) 4 -- 3 MODE (R/W)
(R/W) (R/W*2) 1 SOE (R/W) 0 SCOE (R/W) Initial value ----0000B
*1: Only "0" can be written. *2: Only "1" can be written. Reading always returns "0". This register controls the transfer operation mode of the serial I/O. The following describes the function of each bit. (a) [bit 3] Serial mode selection bit (MODE) This bit selects the conditions for starting operation from the halted state. Changing the mode during operation is prohibited. MODE 0 1 Operation Start when STRT is set to "1". [Initial value] Start on reading from or writing to the serial data register.
The bit is initialized to "0" by a reset. The bit is readable and writable. Set to "1" when using the intelligent I/O service.
37
MB90630A Series
(b) [bit 2] Transfer direction selection bit (BDS: Bit Direction Select) Selects as follows at the time of serial data input and output whether the data are to be transferred in the order from LSB to MSB or vice versa. MODE 0 1 (3) Block Diagram LSB-first [Initial value] MSB-first Operation
Internal data bus (MSB-first) D0 to D7 SIN1, 2 SDR (Serial data register) SOT1, 2 Read Write D7 to D0 (LSB-first) Transfer direction selection
SCK1, 2 Control circuit Shift clock counter
Internal clock
2
1
0
SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
38
MB90630A Series
4. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features. * Conversion time: Minimum of 5.2 s per channel (for a 16 MHz machine clock) * Uses RC-type successive approximation conversion with a sample and hold circuit. * 10-bit resolution * Eight program-selectable analog input channels Single conversion mode : Selectively convert a one channel. Scan conversion mode : Continuously convert multiple channels. Maximum of 8 programselectable channels. Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) * An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. * Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) Register Configuration The A/D converter has the following registers.
15 ADCS2 ADCR2 8 bits
8
7 ADCS1 ADCR1 8 bits
0
bit Address: 000036H bit Address: 000037H bit Address: 000038H bit Address: 000039H
7 MD1 15 BUSY 7 7 15 --
6 MD0 14 INT 6 6 14 --
5 ANS2 13 INTE 5 5 13 --
4 ANS1 12 PAUS 4 4 12 --
3 ANS0 11 STS1 3 3 11 --
2 ANE2 10 STS0 2 2 10 --
1 ANE1 9 STRT 1 1 9 9
0 ANE0 8 DA 0 0 8 8 Data register (ADCR1, ADCR2) Control status register (ADCS1, ADCS2)
39
MB90630A Series
(2) Block Diagram
AV CC
AVRH AVRL
AV SS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Successive approximation register
Comparator
Sample and hold circuit
Decoder
Data register ADCR1, 2
A/D control register 1 A/D control register 2 ADCS1, 2 ADTG PPG01 Trigger activation Timer activation Operating clock
Prescaler
40
Data bus
MB90630A Series
5. D/A Converter
This block is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The D/A control register controls the output of the two D/A converters independently. (1) Register Configuration
bit Address: 00003AH bit Address: 00003BH bit Address: 00003CH bit Address: 00003DH 7 DA07 15 DA17 7 -- 15 -- 6 DA06 14 DA16 6 -- 14 -- 5 DA05 13 DA15 5 -- 13 -- 4 DA04 12 DA14 4 -- 12 -- 3 DA03 11 DA13 3 -- 11 -- 2 DA02 10 DA12 2 -- 10 -- 1 DA01 9 DA11 1 -- 9 -- 0 DA00 8 DA10 0 DAE0 8 DAE1 D/A converter data register 0 (DAT0) D/A converter data register 0 (DAT1) D/A control register 0 (DACR0) D/A control register 1 (DACR1)
(2) Block Diagram
F2MC-16 bus
DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00
DVR DA17 2R DA16 2R DA15 R DA07
DVR
2R DA06 2R DA05
R
R
R
DA11 2R DA10 R
DA01 2R DA00 R
2R 2R DAE1 Standby control
2R 2R DAE0 Standby control
DA output channel 1
DA output channel 0
41
MB90630A Series
6. 8/16-bit PPG
This block is an 8-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. * 8-bit PPG output in two channels independent operation mode: Two independent PPG output channels are available. * 16-bit PPG output operation mode : One 16-bit PPG output channel is available. * 8+8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. * PPG output operation : Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register Configuration
PPG0 operation mode control Address: channel 0 000044H Read/write Initial value PPG1 operation mode control Address: channel 1 000045H Read/write Initial value PPG0, 1 output control register Address: channel 0,1 000046H Read/write Initial value
7 PEN0 (R/W) (0) 15 PEN1 (R/W) (0) 7 PCS2 (R/W) (0) 15
6 -- (--) (X) 14 -- (--) (X) 6 PCS1 (R/W) (0) 14
5 PE00 (R/W) (0) 13 PE10 (R/W) (0) 5 PCS0 (R/W) (0) 13
4 PIE0 (R/W) (0) 12 PIE1 (R/W) (0) 4 PCM2 (R/W) (0) 12
3 PUF0 (R/W) (0) 11 PUF1 (R/W) (0) 3 PCM1 (R/W) (0) 11
2 -- (--) (X) 10 MD1 (R/W) (0) 2 PCM0 (R/W) (0) 10
1 -- (--) (X) 9 MD0 (R/W) (0) 1 PE11 (R/W) (0) 9
0
Reserved
PPGC0
(--) (1) 8
Reserved
PPGC1
(--) (1) 0 PE01 (R/W) (0) 8 PRLH0, 1 PPGOE
Reload register H Address: channel 0 000041H channel 1 000043H Read/write Initial value
(R/W) (X) 7
(R/W) (X) 6
(R/W) (X) 5
(R/W) (X) 4
(R/W) (X) 3
(R/W) (X) 2
(R/W) (X) 1
(R/W) (X) 0 PRLL0, 1
Reload register L Address: channel 0 000040H channel 1 000042H Read/write Initial value
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
42
MB90630A Series
(2) Block Diagram * 8/16-bit PPG (channel 0)
PPG00 output enable
Peripheral clock divided by 16 Peripheral clock divided by 8 Peripheral clock divided by 4 Peripheral clock divided by 2 Peripheral clock
PPG00 PPG01
PPG01 output enable A/D converter PPG0 output latch Invert Clear PEN0
PCNT (Down-counter) Count clock selection Timebase counter output Main clock divided by 512 L/H select Reload
S RQ
IRQ
channel 1-borrow L/H selector
PRLL0
PRLBH0 PIE 0
PRLH0
PUF0 L-side data bus H-side data bus
PPGC0 (Operation mode control)
43
MB90630A Series
* 8/16-bit PPG (channel 1)
PPG10 output enable
Peripheral clock divided by 16 Peripheral clock divided by 8 Peripheral clock divided by 4 Peripheral clock divided by 2 Peripheral clock
PPG10 PPG11
PPG11 output enable UART PPG1 output latch Invert Clear
Count clock selection PEN1
PCNT (Down-counter) channel 0-borrow Timebase counter output Main clock divided by 512 L/H select Reload L/H selector
S RQ
IRQ
PRLL1
PRLBH1 PIE
PRLH1
PUF L-side data bus H-side data bus
PPGC1 (Operation mode control)
44
MB90630A Series
7. 8/16-bit Up/Down Counter/Timer
This block is an up/down counter/timer and consists of six event input pins, two 8-bit up/down counters, two 8bit reload/compare registers, and their control circuits. (1) Main Functions * The 8-bit count register can count in the range 0 to 256D (or 0 to 65535D in 1 x 16-bit operation mode). * The count clock selection can select between four different count modes. Count modes Timer mode Up/down counter mode Phase difference count mode (x 2) Phase difference count mode (x 8) * Two different internal count clocks are available in timer mode. Count clock (at 16 MHz operation) 125 ns (8 MHz: Divide by 2) 1.0 s (1 MHz: Divide by 8) * In up/down count mode, you can select which edge to detect on the external pin input signal. Detected edge Detect falling edges Detect rising edges Detect both rising and falling edges Edge detection disabled * Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply. * Two different functions can be selected for the ZIN pin. ZIN pin Counter clear function Gate function * Compare and reload functions are available and can be used either independently or together. A variablewidth up/down count can be performed by activating both functions. Compare/reload function Compare function (Output an interrupt when a compare occurs.) Compare function (Output an interrupt and clear the counter when a compare occurs.) Reload function (Output an interrupt and reload when an underflow occurs.) Compare/reload function (Output an interrupt and clear the counter when a compare occurs. Output an interrupt and reload when an underflow occurs.) Compare/reload disabled * Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set independently. * The previous count direction can be determined from the count direction flag. * An interrupt can be generated when the count direction changes.
45
MB90630A Series
(2) Register Configuration The 8/16-bit up/down counter/timer has the following registers.
15 UDCR1 RCR1 Reversed area CCRH0 Reversed area CCRH1 8 bits
8
7 UDCR0 RCR0 CSR0 CCRL0 CSR1 CCRL1 8 bits
0
bit Address: 000070H bit Address: 000071H bit Address: 000072H bit Address: 000073H bit Address: 000074H 000078H bit Address: 000076H 00007AH bit Address: 000077H bit Address: 00007BH
7 D07 15 D17 7 D07 15 D17 7 CSTR 7 -- 15
6 D06 14 D16 6 D06 14 D16 6 CITE 6 CTUT 14
5 D05 13 D15 5 D05 13 D15 5 UDIE 5 UCRE 13 CFIE 5 CFIE
4 D04 12 D14 4 D04 12 D14 4 CMPF 4 RLDE 12 CLKS 4 CLKS
3 D03 11 D13 3 D03 11 D13 3 OVFF 3
2 D02 10 D12 2 D02 10 D12 2 UDFF 2
1 D01 9 D11 1 D01 9 D11 1 UDF1 1
0 D00 8 D10 0 D00 8 D10 0 UDF0 0 CGE0 8 CES0 0 CES0
Up/down count register channel 0 (UDCR0) Up/down count register channel 1 (UDCR1) Reload compare register channel 0 (RCR1) Reload compare register channel 1 (RCR1) Counter status register channel 0, 1 (CSR0, 1) Counter status register channel 0, 1 (CCRL0, 1) Counter control register channel 0 (CCRH0) Counter control register channel 1 (CCRH1)
UDCC CGSC CGE1 11 10 9 CES1 1 CES1
M16E CDCF 7 -- 6 CDCF
CMS1 CMS0 3 2
CMS1 CMS0
46
MB90630A Series
(3) Block Diagram * 8/16-bit Up/Down Counter/Timer (channel 0)
Data bus
8 bits CGE1 CGE0 C/GS
RCR0 (reload/compare regiater 0)
CTUT
ZIN0
Edge or level detection
Reload control
UCRE
RLDE
UDCC
Counter clear 8 bits UDCR0 (Up/down count regiater 0) Carry CMPF
CES1 CES0 CMS1 CMS0 CITE AIN0 BIN0 Count clock UDF1 UDF0 CDCF CFIE Interrupt output
UDFF OVFF UDIE
Up/down count clock selection
Prescaler
CSTR
CLKS
47
MB90630A Series
* 8/16-bit Up/Down Counter/Timer (channel 1)
Data bus
8 bits CGE1 CGE0 C/GS
RCR1 (reload/compare register 1)
CTUT
ZIN1
Edge or level detection
Reload control
UCRE
RLDE
UDCC
Counter clear 8 bits UDCR1 (Up/down count register 1) CMPF UDFF OVFF
CMS1 CMS0 CES1 CES0 EN16 Carry CITE UDIE
Count clock
AIN1 BIN1 Up/down count clock selection UDF1 UDF0 CDCF CFIE
Prescaler
CSTR
Interrupt output
CLKS
48
MB90630A Series
8. Clock Output Control Register
The clock output outputs the divided machine clock. (1) Register Configuration
bit Clock control register Address: 0003EH Read/write Initial value 7 -- 6 -- 5 -- 4 -- 3 CKEN (R/W) (0) 2 FRQ2 (R/W) (0) 1 FRQ1 (R/W) (0) 0 FRQ0 (R/W) (0) CLKR
(--)
(--)
(--)
(--)
(a) [bit 3] CKEN CKOT output enable bit MODE 0 1 Operate as a standard port. Operate as the CKOT output. Operation
(b) [bits 2, 1, 0] FRQ2, FRQ1, FRQ0 These bits select the output frequency of the clock. FRQ2 0 0 0 0 1 1 1 1 FRQ1 0 0 1 1 0 0 1 1 FRQ0 0 1 0 1 0 1 0 1 Output clock /2
1
= 16 MHz 125 ns 250 ns 500 ns 1 s 2 s 4 s 8 s 16 s
= 8 MHz 250 ns 500 ns 1 s 2 s 4 s 8 s 16 s 32 s
= 4 MHz 500 ns 1 s 2 s 4 s 8 s 16 s 32 s 64 s
/22 /23 /2
4
/25 /26 /2
7
/28
49
MB90630A Series
9. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels ("H" and "L") are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on "H" and "L" levels can be selected, giving a total of four types. (1) Register Configuration
bit Address: 000030H bit Address: 000031H bit Address: 000032H bit Address: 000033H
7 EN7 15 ER7 7 LB3 15 LB7
6 EN6 14 ER6 6 LA3 14 LA7
5 EN5 13 ER5 5 LB2 13 LB6
4 EN4 12 ER4 4 LA2 12 LA6
3 EN3 11 ER3 3 LB1 11 LB5
2 EN2 10 ER2 2 LA1 10 LA5
1 EN1 9 ER1 1 LB0 9 LB4
0 EN0 8 ER0 0 LA0 8 LA4
Interrupt/DTP enable register (ENIR) Interrupt/DTP source register (EIRR) Request level setting register (ELVR) Request level setting register (ELVR)
(2) Block Diagram
4
Interrupt/DTP enable register 4
F2MC-16 bus
4
Gate
Request F/F
Edge detect circuit
Request input
4
Interrupt/DTP source register
8
Request level setting register
50
MB90630A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, four output compare, and two input capture modules. Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs and to measure input pulse widths and external clock periods. (1) A Summary of Each Function * 16-bit free-run timer (x 1) The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the timer/counter is used as the base time for the input capture and output compare. (a) The operating clock for the counter can be selected from four different clocks. Four internal clocks (/4, /16, /32, /64) (b) Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs (the appropriate mode must be set for a compare match). (c) The counter can be initialized to 0000H by a reset, software clear, or compare match with compare register 0. * Output compare (x 4) The output compare consists of two 16-bit compare registers, compare output latches, and control registers. The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches the compare register value. (a) The four compare registers can be operated independently. Each compare register has a corresponding output pin and interrupt flag. (b) The four compare registers can be paired to control the output pins. Invert the output pins using the four compare registers. (c) Initial values can be set for the output pins. (d) An interrupt can be generated when a compare match occurs. * Input capture (x 2) The input capture consists of two independent external input pins, their corresponding capture registers, and a control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt generated when the specified edge is detected on the signal from the external input pin. (a) The edge to detect on the external input signal is selectable. Detection of rising edges, falling edges, or either edge can be specified. (b) The two input capture channels can operate independently. (c) An interrupt can be generated on detection of the specified edge on the external input signal. The input capture interrupt can activate the intelligent I/O service.
51
MB90630A Series
(2) Register Configuration for the Entire 16-bit I/O Timer * 16-bit free-run timer
bit 000066H 000068H 15 TCDT TCCS 0 Timer data register Timer control status register
* 16-bit output compare
bit 000050, 52, 54, 56H 000058, 5AH OCS1/3 15 OCCP0 to 3 OCS0/2 0 Compare register channel 0 to 3 Compare control status register channel 0, 2
* 16-bit input capture
bit 000060, 62H 000064H 15 IPCP0 to 1 ICS 0 Input capture register channel 0, 2 Input capture control status register
* Overall Block Diagram of the 16-bit I/O timer
Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Compare register 0 Output compare 1 bus Compare register 1 Output compare 2 Compare register 2 Output compare 3 Compare register 3 Input capture 0 Capture register 0
Edge selection
To each block
TQ
OUT 0
TQ
OUT 1
TQ
OUT 2
TQ
OUT 3
IN 0
Capture register 1
Edge selection
IN 1
52
MB90630A Series
(3) 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up-counter and a control status register. The count value of the timer is used as the base time for the input capture and output compare. (a) The count clock can be selected from four different clocks. (b) Interrupts can be generated when a counter value overflow occurs. (c) Depending on the mode setting, the counter can be initialized when a match occurs with compare register 0 of the output compare. * Register Configuration
bit 000066H 000068H
15 TCDT TCCS
0 Timer data register Timer/counter control status register
* Block Diagram
Interrupt request
IVF
IVFE STOP MODE CLR
CLK1 CLK0
Divider
bus
Comparator 0
16-bit up-counter
Clock
Count value output T15 to T00
53
MB90630A Series
* Register Details Data Register
bit Address: 000067H Read/write Initial value 15 T15 (R/W) (0) 14 T14 (R/W) (0) 13 T13 (R/W) (0) 12 T12 (R/W) (0) 11 T11 (R/W) (0) 10 T10 (R/W) (0) 9 T09 (R/W) (0) 8 T08 (R/W) (0)
bit Address: 000066H Read/write Initial value
7 T07 (R/W) (0)
6 T06 (R/W) (0)
5 T05 (R/W) (0)
4 T04 (R/W) (0)
3 T03 (R/W) (0)
2 T02 (R/W) (0)
1 T01 (R/W) (0)
0 T00 (R/W) (0)
The count value of the 16-bit free-run timer can be read from this register. The count is cleared to "0000H" by a reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted (STOP = "1"). Always use word access. The 16-bit free-run timer is initialized by the following. (a) Reset (b) The clear bit (CLR) of the control status register (c) A match between the timer/counter value and compare register 0 of the output compare (if the appropriate mode is set)
54
MB90630A Series
(4) Output Compare The output compare consists of 16-bit compare registers, compare output pins, and a control register. The module can invert the output level and generate an interrupt when the 16-bit free-run timer value matches a compare register value. (a) The two compare registers can be operated independently. The output compare can also be set to control pin output using two compare registers. (b) The initial value of the output pins can be set. (c) An interrupt can be generated when a compare match occurs. * Register Configuration
bit 000050, 52, 54, 56H 15 OCCP0 to 3 0 Compare registers channel 0 to 3
bit 000058, 59, 5A, 5BH
15 OCSX OCSX
0
Compare control status registers channel 0 to 3 X = 0 to 3
* Block Diagram
16-bit timer/counter value (T15 to T00)
OUT0 (OUT2)
Compare control
TQ
OTEO
Compare regiater 0 (2) CMOD
16-bit timer/counter value (T15 to T00)
OUT1 (OUT3)
bus
Compare control
TQ
OTE1
Compare regiater 1 (3) ICP1 Controller Control blocks ICP0 ICE1 ICE0 Compare 1 interrupt (3) Compare 0 interrupt (2)
55
MB90630A Series
(5) Input Capture The function of this module is to store the value of the 16-bit free-run timer in a register when the specified edge (rising, falling, or either edge) is detected on the external input signal. The module can also generate an interrupt on detection of the edge. The input capture contains input capture data registers and a control register. Each input capture has a corresponding external input pin. (a) Three different types of edge detection can be selected. Rising edges (), falling edges (), or either edge ( ). (b) An interrupt can be generated on detection of the specified edge on the external input. * Register Configuration (for the entire input capture)
bit 000060, 62H 15 IPCX 0 Input capture data register X = 0 to 1
bit 000064H
7 ICSX
0 Input capture control status register X = 0 to 1
* Block Diagram
Capture data register 0
Edge detection
IN 0
16-bit timer/counter value (T15 to T00) bus
EG11 EG10 EG01 EG00
Capture data register 1
Edge detection
IN 1
ICP1
ICP0
ICE1
ICE0 Interrupt Interrupt
56
MB90630A Series
* Register Details Input capture data register
bit 000060, 62H Read/write Initial value 15 CP15 (R) (X) 14 CP14 (R) (X) 13 CP13 (R) (X) 12 CP12 (R) (X) 11 CP11 (R) (X) 10 CP10 (R) (X) 9 CP09 (R) (X) 8 CP08 (R) (X)
bit
7 CP07
6 CP06 (R) (X)
5 CP05 (R) (X)
4 CP04 (R) (X)
3 CP03 (R) (X)
2 CP02 (R) (X)
1 CP01 (R) (X)
0 CP00 (R) (X)
Read/write Initial value
(R) (X)
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)
57
MB90630A Series
11. Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase counter as its clock source, a control register, and a watchdog reset controller. The following block diagram shows the structure of both the watchdog timer and timebase timer (see "12. Timebase Timer"). (1) Block Diagram
WTE Output enable WT1 WT0 Selector 2-bit counter Reset control Reset
Timebase counter f/2 1 2 Clear Power-on reset STOP mode Clear control Selectror TBR Clear TBC1 TBC0 1/2 16 to 1/2 18 (Timebase division output) I OS
2
.........
1 212
1 213
1 214
1 215
1 216
1 217
1 218
TBIE TBOF
IRQ
OSC1 Selectror OSC0 Oscillation stabilization delay completion signal
(2) Register Configuration
bit Address: 0000A8H
7 PONR
6 STBR
5 WRST
4 ERST
3 SRST
2 WTE
1 WT1
0 WT0 Watchdog timer control register (WDTC)
58
MB90630A Series
12. Timebase Timer
The timebase timer consists of an 18-bit timebase counter (which divides the system clock) and a control register. The carry signal of the timebase counter can generate a fixed period interrupt. All bits of the timebase counter are cleared to zero at power-on, when stop mode is set, or by software (by writing "0" to the TBR bit). The timebase counter continuously increments while an oscillation is input. The timebase counter is also used as the clock source for the watchdog timer and as a timer for the oscillation stabilization delay time. (1) Block Diagram See "(1) Block diagram" in "11. Watchdog Timer" for the block diagram of the timebase timer. (2) Register Configuration
bit Address: 0000A9H 15
Reserved
14 --
13 --
12 TBIE
11 TBCF
10 TBR
9 TBC1
8 TBC0 Timebase timer control register (TBTC)
(3) Register Details * TBTC (Timebase timer control register)
bit Address: 0000A9H 15
Reserved
14 --
13 --
12 TBIE (R/W)
11 TBCF (R/W)
10 TBR (W)
9 TBC1 (R/W)
8 TBC0 (R/W)
Initial value X--00000B
(W)
(a) [bit 15] Reserved A reserved bit. Always set to "1" when writing data to the register. (b) [bit 12] TBIE Interval interrupt enable bit for the timebase timer. The interrupt is enabled when TBIE is "1" and disabled when TBIE is "0". Initialized to "0" by a reset. The bit is readable and writable. (c) [bit 11] TBOF Interrupt request flag for the timebase timer. An interrupt request is generated if TBCF goes to "1" when TBIE is "1". The bit is set to "1" at fixed intervals set by the TBC1 and 0 bits. Clear by writing "0", transition to stop or hardware standby mode, or a reset. Writing "1" has no meaning. Read as "1" by read-modify-write instructions. (d) [bit 10] TBR Clears all bits of the timebase counter to "0". Writing "0" to the TBR bit clears the timebase counter. Writing "1" to the TBR bit is meaningless. Reading from the TBR bit results in "1". (e) [bit 9, 8] TBC1, 0 Set a timebase timer interval. The bits are initialized to "00" by resetting. These bits are readable and writable. Setting of timebase timer interval TBC1 0 0 1 1 TBC0 0 1 0 1 Interval time when base frequency is 4 MHz 1.024 ms 4.096 ms 16.384 ms 131.072 ms
59
MB90630A Series
13. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins required to extend the CPU's address/data bus outside the device. (1) Register Configuration
bit Auto-ready function selection register 0000A5H Address: Read/write Initial value
15 ICR1 (W) (0)
14 ICR0 (W) (0)
13 HMR1 (W) (1)
12 HMR0 (W) (1)
11 -- (--) (--)
10 -- (--) (--)
9 LMR1 (W) (0)
8 LMR0 (W) (0) ARSR
bit External address output control register Address: 0000A6H Read/write Initial value
7 E23 (W) (0)
6 E22 (W) (0)
5 E21 (W) (0)
4 E20 (W) (0)
3 E19 (W) (0)
2 E18 (W) (0)
1 E17 (W) (0)
0 E16 (W) (0) HACR
bit Bus control signal selection register 0000A7H Address: Read/write Initial value
15 CKE (W) (0)
14 RYE (W) (0)
13 HDE (W) (0)
12 ICBS (W) (0)
11 HMBS (W) (1/0)
10 WRE (W) (0)
9 LMBS (W) (0)
8 -- (--) (--) EPCR
(2) Block Diagram
P3 P3 P0
P0 P0 data
P1
P2
P0 direction
RB
Data control
Address control
Access control
Access control
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MB90630A Series
4. Low-Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Delay Time, and Clock Multiplier Function)
The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are classified as low power consumption modes. In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock). The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the operating clock. In PLL sleep mode and main sleep mode, the CPU's operating clock only is stopped and other elements continue to operate. In timer mode, only the timebase timer operates. Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum power consumption. The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal memory, internal resource, or external bus access is performed. This function reduces power consumption by lowering the CPU execution speed while still providing a high-speed clock to internal resources. The PLL clock multiplier ratio can be set to 1, 2, 3, or 4 by the CS1, 0 bits. The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop mode or hardware standby mode. (1) Register Configuration
bit Low-power consumption mode register Address: 0000A0H Read/write Initial value
7 STP (W) (0)
6 SLP (W) (0)
5 SPL (R/W) (0)
4 RST (W) (1)
3
Reserved
2 CG1 (R/W) (0)
1 CG0 (R/W) (0)
0
Reserved
LPMCR
(--) (1)
(--) (0)
bit Clock select register Address: 0000A1H Read/write Initial value
15
Reserved
14 MCM (R) (1)
13 WS1 (R/W) (1)
12 WS0 (R/W) (1)
11
Reserved
10 MCS (R/W) (1)
9 CS1 (R/W) (0)
8 CS0 (R/W) (0) CKSCR
(--) (1)
(--) (1)
61
MB90630A Series
(2) Block Diagram * Low-Power Consumption Control Circuit and Clock Generator
CKSCR MCM MCS CKSCR CS1 CS0 LPMCR CG1 F2MC-16 bus CG0 LPMCR SLP STP Standby control circuit RST release HSTactivate
Cycle selection circuit for the CPU intermittent operation function
PLL multiplier circuit 1 2 3 4 1/2
Main clock (OSC oscillator) CPU clock CPU clock generator 0/9/17/33 intermittent cycle selection
CPU clock selector
Peripheral clock generator
Peripheral clock
HST pin Interrupt request or RST Oscillation stabilization delay time selector 24 213 215 218 Clock input Timebase timer 2
12
CKSCR OSC1 OSC0 LPMCR SPL
Timebase clock
16
2
14
2
2
19
Pin high impedance control circuit
Pin HI-Z
LPMCR RST
Internal reset generator
RST pin Internal RST To watchdog timer WDGRST
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MB90630A Series
* State Transition Diagram for Clock Selection
Power-on
Main MCS=1 MCM=1 CS1/0=XX
(1)
MainPLLX MCS=0 MCM=1 (6) CS1/0=XX
(2)
(3) (7)
PLL1Main MCS=1 MCM=0 CS1/0=00 PLL 1 multiplier MCS=0 MCM=0 CS1/0=00
(4) (6)
(7)
PLL2Main MCS=1 (7) MCM=0 CS1/0=01
(6)
PLL 2 multiplier MCS=0 MCM=0 CS1/0=01
PLL3Main (7) MCS=1 MCM=0 CS1/0=10
(5) (6)
PLL 3 multiplier MCS=0 MCM=0 CS1/0=10
PLL4Main MCS=1 MCM=0 CS1/0=11
(6)
PLL 4 multiplier MCS=0 MCM=0 CS1/0=11
(1) MCS bit cleared (2) PLL clock oscillation stabilization delay complete and CS1/0="00" (3) PLL clock oscillation stabilization delay complete and CS1/0="01" (4) PLL clock oscillation stabilization delay complete and CS1/0="10" (5) PLL clock oscillation stabilization delay complete and CS1/0="11" (6) MCS bit set (including a hardware standby or watchdog reset) (7) PLL clock and main clock synchronized timing
63
MB90630A Series
5. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16L CPU can be generated and cleared by software using this module. (1) Register Configuration
bit Address: 00009FH 15 -- 14 -- 13 -- 12 -- 11 -- 10 -- 9 -- 8 R0 Delayed interrupt request register (DIRR)
(2) Register Details Delayed interrupt request register (DIRR)
bit Address: 00009FH 15 -- 14 -- 13 -- 12 -- 11 -- 10 -- 9 -- 8 R0 (R/W) Initial value -------0B
The DIRR register controls generation and clearing of delayed interrupt requests. Writing "1" to the register generates a delayed interrupt request. Writing "0" to the register clears the delayed interrupt request. The register is set to the interrupt cleared state by a reset. Either "0" or "1" can be written to the reserved bits. However, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access. (3) Block Diagram
Delayed interrupt generate/clear decoder F2MC-16 bus
Interrupt latch
64
MB90630A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter VCC Power supply voltage AVCC*
1
Symbol
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 -- VCC + 0.3 VCC + 0.3 15 50 100 50 -15 -50 -100 -50 +400 +85 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mW C C
Remarks
AVRH, AVRL*1 Program voltage Input voltage*
2
VPP VI VO IOL IOLAV
Output voltage*2 "L" level (maximum) output current*3 "L" level (average) output current*
4
"L" level total (maximum) output current IOL "L" level total (average) output current*5 IOLAV "H" level (maximum) output current* "H" level (average) output current*4
5 3
IOH IOHAV IOHAV Pd TA Tstg
"H" level total (maximum) output current IOH "H" level total (average) output current* Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5:
AVCC, AVRH, and AVRL must not exceed VCC. Similarly, it must not exceed AVRH and AVRL. VI and VO must not exceed VCC + 0.3 V. The maximum output current must not be exceeded at any individual pin. The average output current is the rating for the current from an individual pin averaged over 100 ms. The average total output current is the rating for the current from all pins averaged over 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB90630A Series
2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Power supply voltage Symbol VCC VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage Operating temperature VILS VILM TA Value Min. 2.7 2.7 0.7 VCC 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 Max. 5.5 5.5 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 +85 Unit V V V V V V V V C Other than VILS Hysteresis inputs Remarks For normal operation To maintain statuses in stop mode Other than VIHS Hysteresis inputs
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
66
MB90630A Series
3. DC Characteristics
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage VILS VILM -- -- Pin name Condition VCC = +5.0 V10% -- VCC = +5.0 V10% -- VCC = +4.5 V10% IOH = -4.0 mA VCC = +2.7 V IOH = -1.6 mA VCC = +4.5 V10% IOH = -4.0 mA VCC = +2.7 V IOH = -2.0 mA Pull-up resistor Rpull ICC ICCS Power supply current*2 ICC ICCS ICCH Other than VCC and VSS P73, 74 P86, 87 P50 to P57 VCC VCC RST -- VCC = +5.0 V10% FC = 16 MHz VCC = +3.0 V10% FC = 10 MHz VCC = +5.0 V10% -- VCC = 5.5 V VSS < VI < VCC -- Value Min. 0.7 VCC 0.8 VCC VCC - 0.3 0.7 VCC 0.8 VCC VSS - 0.3 VCC - 0.5 Typ. -- -- -- -- -- -- -- Max. VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VSS + 0.3 -- Unit Remarks V V V V V V V *1 *1
"H" level output voltage VOH
--
VCC - 0.3
--
--
V
--
--
0.4
V
"L" level output voltage VOL
--
-- 22 -- -- -- -- --
-- -- 60 20 15 10 --
0.4 110 80 35 40 15 20
V k mA mA mA mA A
Input pin capacitance
CIN
--
10
--
pF A A
Input leak current Leak current for open-drain outputs
IIL Ileak
-10 --
-- 0.1
10 10
*1: Hysteresis input pins: RST, HST *2: Current values are provisional and are subject to change without notice to allow for improvements to the characteristics and similar.
67
MB90630A Series
4. AC Characteristics
(1) Clock Timing * When VCC = 5.0 V10% Pin name X0, X1 X0, X1 X0 X0 -- -- (VCC = 4.5 V to +5.0 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- -- 3 62.5 10 -- 1.5 62.5 16 333 -- 5 16 333 MHz ns ns ns MHz ns The duty ratio should be in the range 30 to 70%
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time
Symbol FC tC PWH, PWL tcr, tcf fCP tCP
* When VCC = 2.7 V (min.) Pin name X0, X1 X0, X1 X0 X0 -- -- (VCC = 4.5 V to +5.0 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- -- 3 100 20 -- 1.5 100 10 333 -- 5 8 333 MHz ns ns ns MHz ns The duty ratio should be in the range 30 to 70%
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time
Symbol FC tC PWH, PWL tcr, tcf fCP tCP
* Clock Timing
tC 0.8 V CC 0.2 V CC P WL t cf t cr
P WH
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MB90630A Series
* PLL Operation Assurance Range
Relationship between the internal operating clock frequency and suply voltage Normal operation range 5.5 VCC Voltage (V)
4.5
3.3 2.7 PLL operation assurance range
1.5
3
8 Internal clock FCP (MHz)
16
Relationship between the oscillation frequency and internal operating clock frequency Multiply Multiply by 4 by 3 16 No multiplier Multiply by 2 Internal clock FCP (MHz) 12 Multiply by 1
9 8
4
34
8
16 Oscillation clock FC (MHz)
24
32
Note: Low voltage operation down to 2.7 V is also assured for the evaluation tools.
The AC characteristics are for the following measurement reference voltages. * Input Signal Waveform
Hysteresis input pins 0.8 V CC 0.2 V CC
* Output Signal Waveform
Output pins 2.4 V 0.8 V
Other than hysteresis or MD input pins 0.7 V CC 0.3 V CC
69
MB90630A Series
(2) Clock Output Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. VCC = 5.0 V10% 62.5 20 -- -- ns ns
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
Pin name CLK
t CYC t CHCL 2.4 V CLK 0.8 V 2.4 V
(3) Reset and Hardware Standby Inputs Pin name RST -- Hardware standby input time tHSTL HST 4 -- (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. 4 -- Machine cycle Machine cycle
Parameter Reset input time
Symbol tRSTL
RST HST 0.2 V CC
t RSTL, t HSTL
0.2 V CC
70
MB90630A Series
(4) Power-on Reset (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. VCC VCC -- -- 1 30 -- ms ms
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Note: The above values are the values required for a power-on reset.
tR V CC 2.25 V 0.2 V
Abrupt changes in the power supply voltage may cause a power-on reset. When changeing the power supply voltage during operation, suppress variations in the voltage and ensure that the voltage rises smoothly, as shown in the following figure. Also, do not use the PLL clock when varying the voltage. However, the supply voltage can be changed when using the PLL clock if the voltage drops by less than 1 mV/s. 5.0 V V CC 2.7 V Holding RAM data V SS The gradient should be no more than 50 mV/ms.
71
MB90630A Series
(5) Bus Timing (Read) (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. ALE Multiplexed address Multiplexed address Multiplexed address Multiplexed address RD D15 to D00 RD, ALE Address, RD Address, CLK RD, CLK -- tCP/2 -20 tCP/2 -25 tCP/2 -15 tCP -15 -- 3 tCP/2 -20 -- 0 0 tCP/2 -15 tCP/2 -10 tCP/2 -20 tCP/2 -20 -- -- -- ns -- 5 tCP/2 -60 -- 3 tCP/2 -60 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns
Parameter ALE pulse width Valid address ALE time ALE address valid time Valid address RD time
Valid address valid data input
Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tAVDV tRHLH tRHAX tAVCH tRLCH
RD pulse width RD valid data input RD data hold time
Valid address valid data input
RD ALE time RD address valid time Valid address CLK time RD CLK time
t AVCH CLK 2.4 V
t RLCH 2.4 V
t AVLL ALE 2.4 V t LHLL t AVRL
t LLAX 2.4 V 0.8 V t RLRH
t RHLH 2.4 V
RD
2.4 V 0.8 V t RHAX
A19 to A16
2.4 V 0.8 V t RLDV t AVDV
2.4 V 0.8 V t RHDX 2.4 V 0.8 V 0.7 V CC 0.3 V CC Read data 0.7 V CC 0.3 V CC
AD15 to AD00
2.4 V Address 0.8 V
72
MB90630A Series
(6) Bus Timing (Write) (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Valid address WR time Valid address RD time WR pulse width RD pulse width Valid data output WR time WR data hold time WR address valid time WR ALE time WR CLK time Symbol tAVWL tAVRL tWLWH tRLRH tDVWH tWHDX tWHAX tWHLH tWLCH Pin name A19 to A00 A23 to A00 WR RD D15 to D00 D15 to D00 A19 to A00 WR, ALE WRL, WRH, CLK -- Condition Value Min. tCP-15 tCP/2 -15 3 tCP/2 -20 3 tCP/2 -20 3 tCP/2 -20 20 tCP/2 -10 tCP/2 -15 tCP/2 -20 Max. -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns Remarks
t WLCH CLK 2.4 V
t WHLH ALE 2.4 V
t AVWL
t WLWH 2.4 V 0.8 V t WHAX
WR (WRL, WRH)
A19 to A16
2.4 V 0.8 V t DVWH
2.4 V 0.8 V t WHDX 2.4 V 0.8 V
AD15 to AD00
2.4 V 0.8 V
Address
2.4 V 0.8 V
Write data
73
MB90630A Series
(7) Ready Input Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. VCC = 5.0 V 10% RDY VCC = 3.0 V 10% -- 45 70 0 -- -- -- ns ns ns
Parameter RDY setup time RDY hold time
Symbol tRYHS tRYHH
Pin name
Note: Use the auto-ready function if the RDY setup time is too short.
CLK ALE
2.4 V
2.4 V
RD/WR
t RYHS RDY (When one wait states are inserted) 0.2 VCC
t RYHS 0.2 VCC
t RYHS RDY (When wait states are not inserted) 0.8 VCC
t RYHH 0.8 VCC
74
MB90630A Series
(8) Hold Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. HAK HAK -- -- 30 tCP tCP 2 tCP ns ns
Parameter Pin floating HAK time HAK pin valid time
Symbol tXHAL tHAHV
Note: After reading HRQ, more than one cycle is required before changing HAK.
HRQ
HAK
t XHAL Pin High impedance
t HAHV
75
MB90630A Series
(9) UART Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- VCC = +5.0 V 10% tSLOV VCC = +3.0 V 10% VCC = +5.0 V 10% tIVSH VCC = +3.0 V 10% VCC = +5.0 V 10% tSHIX tSHSL tSLSH tSLOV -- VCC = +3.0 V 10% -- -- VCC = +5.0 V 10% VCC = +3.0 V 10% VCC = +5.0 V 10% tIVSH VCC = +3.0 V 10% VCC = +5.0 V 10% tSHIX VCC = +3.0 V 10% 8 tCP -80 -120 100 200 60 120 4 tCP 4 tCP -- -- 60 120 60 120 -- 80 120 -- -- -- -- -- -- 150 200 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 80 pF+1TTL for the external shift clock mode output pin CL = 80 pF+1TTL for the internal shift clock mode output pin
Parameter Serial clock cycle time SCK SOT delay time
Pin Symbol name tSCYC
Valid SIN SCK
SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time
Valid SIN SCK
SCK valid SIN hold time
Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance connected to the pin at testing. * tCP is the machine cycle period (unit: ns).
76
MB90630A Series
* Internal Shift Clock Mode
t SCYC SCK 0.8 V t SLOV SOT 2.4 V 0.8 V t IVSH SIN 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC 2.4 V 0.8 V
* External Shift Clock Mode
t SLSH SCK 0.2 V CC t SLOV SOT 2.4 V 0.8 V t IVSH SIN 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC 0.2 V CC 0.8 V CC t SHSL 0.8 V CC
77
MB90630A Series
(10) I/O Extended Serial Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- VCC = +5.0 V 10% VCC = +3.0 V 10% -- -- VCC = +5.0 V 10% VCC = +3.0 V 10% VCC = +5.0 V 10% VCC = +3.0 V 10% -- -- -- 8 tCP -- -- tCP tCP 230 460 230 460 2 tCP tCP 2 tCP -- 80 160 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns CL = 80 pF+1TTL for the external shift clock mode output pin Max. 2 MHz CL = 80 pF+1TTL for the internal shift clock mode output pin
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Pin Symbol name tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX -- -- -- -- -- -- -- -- --
Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance connected to the pin at testing. * tCP is the machine cycle period (unit: ns). * The values in the table are target values.
78
MB90630A Series
* Internal Shift Clock Mode
t SCYC SCK 0.8 V t SLOV SOT 2.4 V 0.8 V t IVSH SIN 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC 2.4 V 0.8 V
* External Shift Clock Mode
t SLSH SCK 0.2 V CC t SLOV SOT 2.4 V 0.8 V t IVSH SIN 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC 0.2 V CC 0.8 V CC t SHSL 0.8 V CC
79
MB90630A Series
(11) Timer Output Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter SCK TOUT change time Symbol tTO Pin name OUT0 to OUT3 Condition VCC = +5.0 V 10% Value Min. 30 80 Max. -- -- Unit ns ns Remarks
PPG00 to PPG11 VCC = +3.0 V 10%
CLK OUT0 to OUT3 PPG0 to PPG1
2.4 V
2.4 V 0.8 V t TO
(12) Trigger Input Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol tTRGH tTRGL Pin name ATG, IRQ0 to IRQ7 IN0, IN1 Condition Value Min. 5 tCP Max. -- Unit Remarks
Input pulse width
--
ns
0.8 V CC ATG, IRQ0 to IRQ7 IN0, IN1 t TRGH
0.8 V CC 0.2 V CC t TRGL 0.2 V CC
80
MB90630A Series
(13) Up/down Counter (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter AIN input "1" pulse width AIN input "0" pulse width BIN input "1" pulse width BIN input "0" pulse width AIN BIN time BIN AIN time AIN BIN time BIN AIN time BIN AIN time AIN BIN time BIN AIN time AIN BIN time ZIN input "1" pulse width ZIN input "0" pulse width Symbol tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL ZIN0, ZIN1 tZLL 4 tCYL -- ns -- AIN0, AIN1 BIN0, BIN1 Pin name Condition Value Min. 8 tCYL 8 tCYL 8 tCYL 8 tCYL 4 tCYL 4 tCYL 4 tCYL 4 tCYL 4 tCYL 4 tCYL 4 tCYL 4 tCYL 4 tCYL Max. -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
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MB90630A Series
t AHL AIN 0.8 VCC 0.8 VCC 0.2 VCC t AUBU BIN t BUAD 0.8 VCC t ADBD 0.8 VCC
t ALL 0.8 VCC 0.2 VCC t BDAU
0.2 VCC t BHL t BLL
0.2 VCC
t BHL BIN 0.8 VCC 0.8 VCC 0.2 VCC t BUAU BIN t AUBD 0.8 VCC t BDAD 0.8 VCC
t BLL 0.8 VCC 0.2 VCC t ADBU
0.2 VCC t AHL t ALL
0.2 VCC
0.8 VCC
0.8 VCC
ZIN
t ZHL t ZLL 0.2 VCC 0.2 VCC
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MB90630A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Unit Parameter Min. Typ. Max. Resolution Total error Linearity error Differential linearity error Zero transition error Full scale transition error Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Variation between channels -- -- -- -- VOT VFST -- IAIN VAIN -- -- IA IAH IR IRH -- -- -- -- -- AN0 to AN7 AN0 to AN7 -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 -- -- -- -- -1.5 AVRH -3.5 5.12*
1
10 -- -- -- +0.5 AVRL -1.5 -- -- -- -- -- -- 5 -- 200 -- --
10 3.0 2.0 1.5 +2.5 AVRH +0.5 -- -- 10 AVRH AVCC AVRH - 2.7 -- 5*
3
bit LSB LSB LSB LSB LSB s s A V V V mA A A A LSB
8.12*2 -- AVRL AVRL + 2.7 0 -- -- -- -- --
-- 5*3 4
*1: For VCC = +5.0 V 10% and a 16 MHz machine clock *2: For VCC = +3.0 V 10% and an 8 MHz machine clock *3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = +5.0 V). Notes: * The error increases proportionally as |AVRH - AVRL| decreases. * The output impedance of the external circuits connected to the analog inputs should be in the following range. Output impedance of external circuit < approx. 10 k * If the output impedance of the external circuit is too high, the sampling time for the analog voltage may be too short. (Sampling time = 3.8 s (corresponds to 16 MHz internal operation if the multiplier is 4.)) * Model of the Analog Input Circuit
Analog input R ON1 R ON2 R ON3 Sample and hold circuit C 0 Comparator R ON4 C1
RON1 = 1.5 k (approx.) (VCC = 5.0 V) RON2 = 0.5 k (approx.) (VCC = 5.0 V) RON3 = 0.5 k (approx.) (VCC = 5.0 V) RON4 = 0.5 k (approx.) (VCC = 5.0 V) C0 = 60 pF (approx.) C1 = 4 pF (approx.)
Note: The above values are for reference only.
83
MB90630A Series
6. A/D Converter Glossary
* Resolution The change in analog voltage that can be recognized by the A/D converter. If the resolution is 10 bits, the analog voltage can be resolved into 210 = 1024 steps. * Total error The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. * Linearity error The deviation between the actual conversion characteristic of the device and the line linking the zero transition point (00 0000 0000 00 0000 0001) and the full scale transition point (11 1111 1110 11 1111 1111). * Differential linearity error The variation from the ideal input voltage required to change the output code by 1 LSB.
Digital output 11 1111 1111 11 1111 1110
* * * * * * * * * * *
(1LSB x N + V OT)
Linearity error
00 0000 0010 00 0000 0001 00 0000 0000 V OT V FST - V OT 1022 V NT - (1LSB x N + V OT ) 1LSB [LSB] V NT V (N+1)T
Analog input V FST
1LSB =
Linearity error =
Differential linearity error =
V(N+1)T - V NT - 1 [LSB] 1LSB
84
MB90630A Series
7. 8-bit D/A Converter Electrical Characteristics
(VCC = 2.7 to 5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Unit Remarks Min. Typ. Max. -- -0.9 -- -- 8 -- -- 10 8 0.9 1.2 20 bit LSB % S The load capacitance = 20 pF DVSS = VSS = 0.0 V
Parameter Resolution Differential linearity error Absolute accuracy Conversion time Analog reference power supply voltage Reference power supply current (when operating) Reference power supply current (when stopped) Analog output impedance
Symbol Pin name -- -- -- -- -- -- -- --
--
DVRH
VSS + 1.7
--
VCC
V
ID
DVRH
--
1.0
1.5
Current mA consumption at conversion A k Current consumption when stopped
IDH --
DVRH DA0
-- --
-- 28
10 --
Note: DVSS must be connected at VSS = 0.0 V.
85
MB90630A Series
s EXAMPLE CHARACTERISTICS
(1) "H" Level Output Voltage (2) "L" Level Output Voltage
VOH - IOH VOH (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -2 -4 -6
VCC = +2.7 V VCC = +3.0 V VCC = +3.5 V VCC = +4.0 V VCC = +4.5 V VCC = +5.0 V
-8 IOH (mA)
V OL (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2 4
VOL - IOL
VCC = +2.7 V VCC = +3.0 V VCC = +3.5 V VCC = +4.0 V VCC = +4.5 V VCC = +5.0 V
6
8 IOL (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
(4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN - VCC
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
VIN - VCC
TA = +25C
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2
TA = +25C
VIHS VILS
3
4
5
6 VCC (V)
2
3
4
5
6 VCC (V)
VIHS : Threshold when input voltage in hysteresis characteristics is set to "H" level VILS : Threshold when input voltage in hysteresis characteristics is set to "L" level
86
MB90630A Series
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
ICC (mA) 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 3.0 ICC-VCC TA = +25C fcp = 16 MHz fcp = 12.5 MHz ICCS (mA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.0 ICCS-VCC TA = +25C fcp = 16 MHz
fcp = 12.5 MHz
fcp = 8 MHz fcp = 4 MHz
fcp = 8 MHz fcp = 4 MHz
4.0
5.0
6.0 VCC (V)
4.0
5.0
6.0 VCC (V)
IA (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0
IA-AVCC TA = +25C fCP = 16 MHz
IR (mA) 0.30
IR-AVR TA = +25C fCP = 16 MHz
0.20
0.10
0 4.0 5.0 6.0 AVCC (V) 3.0 4.0 5.0 6.0 AVR (V)
(5) Pull-up Resistance
R-VCC R (k) 1000 TA = +25C
100
10 2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0 VCC (V)
87
MB90630A Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
I S T N Z V C RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
88
MB90630A Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b
(Continued)
89
MB90630A Series
(Continued)
Symbol rel ear eam rlst Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * Meaning
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note: The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
90
MB90630A Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing Listed in tables of instructions 1 2 1 1 2 2 0 0
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Note: "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand (c) word (d) long
Number Number Number Number Number Number of of of of cycles access of cycles access of cycles access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4
Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits)
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
91
MB90630A Series
Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 # ~ Transfer Instructions (Byte) [41 Instructions] R G 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) LA HH Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X - - - - - - - - - - - - - - - - - Z Z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1
3 2 A, dir 4 3 A, addr16 2 2 A, Ri 2 2 A, ear 2+ 3+ (a) A, eam 3 2 A, io 2 2 A, #imm8 3 2 A, @A 5 A,@RWi+disp8 2 10 A, @RLi+disp8 3 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
4 2 2+ 5+ (a) 7 2 2+ 9+ (a)
byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 0 2x (b) byte ((A)) (AH) 0 2x (b) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
92
MB90630A Series
Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 dir, A addr16, A SP, A RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 # Transfer Instructions (Word/Long Word) [38 Instructions] ~ R G 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
MOVW AL, AH /MOVW @A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a)
2 0 0 2x (c) word ((A)) (AH) 4 0 2 2x (c) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) 0 (d) 0 0 (d) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
2 4 2 2+ 5+ (a) 0 5 3 0 2 4 2 2+ 5+ (a) 0
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
- - - - -
- - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
93
MB90630A Series
Table 9 Mnemonic ADD A,#imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB A, #imm8 SUB A, dir SUB A, ear SUB A, eam SUB ear, A SUB eam, A SUBC A SUBC A, ear SUBC A, eam SUBDC A ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL #imm32 SUBL SUBL SUBL #imm32 A, ear A, eam A, A, ear A, eam A, Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 R G B Operation LA HH Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - -
0 0 byte (A) (A) +imm8 0 (b) byte (A) (A) +(dir) 1 0 byte (A) (A) +(ear) 0 (b) byte (A) (A) +(eam) 2 0 byte (ear) (ear) + (A) 0 2x (b) byte (eam) (eam) + (A) 0 0 byte (A) (AH) + (AL) + (C) 1 0 byte (A) (A) + (ear) + (C) 0 (b) byte (A) (A) + (eam) + (C) 0 0 byte (A) (AH) + (AL) + (C) 0 0 (decimal) 0 (b) byte (A) (A) -imm8 1 0 byte (A) (A) - (dir) 0 (b) byte (A) (A) - (ear) 2 0 byte (A) (A) - (eam) 0 2x (b) byte (ear) (ear) - (A) 0 0 byte (eam) (eam) - (A) 1 0 byte (A) (AH) - (AL) - (C) 0 (b) byte (A) (A) - (ear) - (C) 0 0 byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (decimal) 0 0 word (A) (AH) + (AL) 1 0 word (A) (A) +(ear) 0 (c) word (A) (A) +(eam) 0 0 word (A) (A) +imm16 2 0 word (ear) (ear) + (A) 0 2x (c) word (eam) (eam) + (A) 1 0 word (A) (A) + (ear) + (C) 0 (c) word (A) (A) + (eam) + (C) 0 0 word (A) (AH) - (AL) 1 0 word (A) (A) - (ear) 0 (c) word (A) (A) - (eam) 0 0 word (A) (A) -imm16 2 0 word (ear) (ear) - (A) 0 2x (c) word (eam) (eam) - (A) 1 0 word (A) (A) - (ear) - (C) 0 (c) word (A) (A) - (eam) - (C)
1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+
2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * *
- - - - - * - - - - - - - * - -
2 6 2 2+ 7+ (a) 0 5 4 0 2 6 2 2+ 7+ (a) 0 5 4 0
0 (d) 0 0 (d) 0
long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
94
MB90630A Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ R G B Operation LA HH - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C RM W - - - - - - - - - - - - - * - * - * - * - * - *
2 2 2 0 byte (ear) (ear) +1 2+ 5+ (a) 0 2x (b) byte (eam) (eam) +1 2 3 2 0 byte (ear) (ear) -1 2+ 5+ (a) 0 2x (b) byte (eam) (eam) -1 2 3 2 0 word (ear) (ear) +1 2+ 5+ (a) 0 2x (c) word (eam) (eam) +1 2 3 2 0 word (ear) (ear) -1 2+ 5+ (a) 0 2x (c) word (eam) (eam) -1 2 7 4 0 long (ear) (ear) +1 2+ 9+ (a) 0 2x (d) long (eam) (eam) +1 2 7 4 0 long (ear) (ear) -1 2+ 9+ (a) 0 2x (d) long (eam) (eam) -1
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ R G 0 1 0 0 0 1 0 0 B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32 LA HH - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C RM W * * * * * * * * * * * - - - - - - - - - - -
1 1 2 2 2+ 3+ (a) 2 2 1 1 2 2 2+ 3+ (a) 3 2
2 6 2 2+ 7+ (a) 0 5 3 0
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
95
MB90630A Series
Table 12 Mnemonic DIVU DIVU ear DIVU eam A A, A, 2 *4 1 0 0 1 0 0 1 0 2+ *5 1 *8 2 *9 2+ *10 1 *11 2 *12 2+ *13 # 1 2 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] ~ *1 *2 R G 0 1 0 B Operation LA HH - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N - - - - - - - - - - - Z - - - - - - - - - - - V * * * * * - - - - - - C RM W * * * * * - - - - - - - - - - - - - - - - -
2+ *3
DIVUW A, ear DIVUW A, eam MULU MULU ear MULU eam A A, A,
0 word (AH) /byte (AL) Quotient byte (AL) Remainder 0 byte (AH) word (A)/byte (ear) *6 Quotient byte (A) Remainder byte (ear) 0 word (A)/byte (eam) Quotient byte (A) Remainder *7 byte (eam) long (A)/word (ear) Quotient word (A) Remainder 0 word (ear) 0 long (A)/word (eam) (b) Quotient word (A) Remainder word (eam) 0 0 byte (AH) *byte (AL) word (A) (c) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
MULUW A MULUW A, ear MULUW A, eam *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
96
MB90630A Series
Table 13 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions] R G B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a)
0 0 1 0 0 (b) 2 0 0 2x (b) 0 0 1 0 0 (b) 2 0 0 2x (b) 0 0 1 0 0 (b) 2 0 0 2x (b)
1 2 0 0 byte (A) not (A) 2 3 2 0 byte (ear) not (ear) 2+ 5+ (a) 0 2x (b) byte (eam) not (eam) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
1 2 0 0 word (A) not (A) 2 3 2 0 word (ear) not (ear) 2+ 5+ (a) 0 2x (c) word (eam) not (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
97
MB90630A Series
Table 14 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions] R G B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LA HH - - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C RM W - - - - - - - - - - - -
2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0
XORL A, ea XORL A, eam
Table 15 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions] R G 0 B 0 Operation byte (A) 0 - (A) LA HH X - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C RM W * * * * * * - - * - - *
2 3 2 0 byte (ear) 0 - (ear) 2+ 5+ (a) 0 2x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2 0 word (ear) 0 - (ear) 2+ 5+ (a) 0 2x (c) word (eam) 0 - (eam)
Table 16 Mnemonic NRML A, R0 # 2 ~ *1 RG 1
Normalize Instruction (Long Word) [1 Instruction] B 0 Operation long (A) Shift until first digit is "1" byte (R0) Current shift count LA HH - - I - S - T - N - Z * V - C RM W - -
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
98
MB90630A Series
Table 17 Mnemonic RORCA ROLC A RORCear RORCeam ROLC ear ROLC eam ASR A, R0 LSR A, R0 LSL A, R0 # 2 2 ~ 2 2 R G 0 0 Shift Instructions (Byte/Word/Long Word) [18 Instructions] B 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Arithmetic right shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) LA HH - - - - - - - - - - - - - - - - - - I - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - * * - * * * * * * * * * * * * * * * * * * - - - - - - - - - * * * * * * * * * - - - * - * - - -
2 3 2+ 5+ 2 (a) 2+ 3 5+ 2 (a) 2 2 *1 *1 *1
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0
ASRWA LSRWA/SHRW A LSLW A/SHLW A ASRWA, R0 LSRWA, R0 LSLW A, R0
1 1 1 2 2 2
2 2 2 *1 *1 *1
0 0 0 1 1 1
0 0 0 0 0 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
** *R -* * * - * * *
* * * * * *
- - - - - -
* * * * * *
- - - - - -
ASRL A, R0 LSRL A, R0 LSLL A, R0
2 2 2
*2 *2 *2
1 1 1
0 0 0
- - -
- - -
- - -
- - -
* * -
* * *
* * *
- - -
* * *
- - -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
99
MB90630A Series
Table 18 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 ~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15 (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15 (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23 LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6
1 (c) 0 2x (c) 0 (c) 0 2x (c) 2 2x (c) 0 *2
CALLP @eam *6 CALLP addr24 *7
2+ 11+ (a) 4 10
0 2x (c)
*1: *2: *3: *4: *5: *6: *7:
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
100
MB90630A Series
Table 19 Mnemonic CBNE A, #imm8, rel CWBNEA, #imm16, rel # ~ RG 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 B 0 0 0 (b) 0 (c) Branch 2 Instructions [19 Instructions] Operation Branch when byte (A) imm8 Branch when word (A) imm16 LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - R R R R * - S - - - - - - - - - - S S S S * - T - - - - - - - - - - - - - - * - N * * * * * * * * * * - - - - * - Z * * * * * * * * * * - - - - * - V * * * * * * * * * * - - - - * - C RM W * * * * * * - - - - - - - - * - - - - - - - - * - * - - - - - -
3 *1 4 *1
CBNE ear, #imm8, rel 4 *2 CBNE eam, #imm8, 4+ *3 9 5 *4 rel* 5+ *3 CWBNEear, #imm16, rel CWBNEeam, #imm16, 3 *5 rel*9 3+ *6 DBNZ ear, rel DBNZ eam, rel 3 *5 3+ *6 DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24 2 3 4 1 1 2 #local8 1 UNLINK RET *7 RETP *8 1 1 5 4 6 20 16 17 20 15 6
Branch when byte (ear) imm8 Branch when byte (eam) 0 imm8 Branch when word (ear) 2x (b) imm16 Branch when word (eam) imm16 0 Branch when byte (ear) = 2x (c) (ear) - 1, and (ear) 0 Branch when byte (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) Branch when word (ear) = 6x (c) (ear) - 1, and (ear) 0 8x (c) Branch when word (eam) = 6x (c) (eam) - 1, and (eam) 0 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt
0 0 0
(c) (c) (d)
-
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
At constant entry, save old frame pointer to stack, set - new frame pointer, and - allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine
*1: *2: *3: *4: *5: *6: *7: *8: *9:
5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
101
MB90630A Series
Table 20 Mnemonic
PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR A AH PS rlst A AH PS rlst @A CCR, #imm8 CCR, #imm8
Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2 RG 0 0 0 *5 0 0 0 *5 B (c) (c) (c) *4 (c) (c) (c) *4 Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
# 1 1 1 2 1 1 1 2 1 2 2 2 2
LA HH - - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - -
I - - - - - - * - * * * - - - - - - - - - - - - - - - - -
S T N Z V C RM W - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 6x (c) Context switch instruction 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
byte (CCR) (CCR) and imm8 byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank
MOV RP, #imm8 MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A
2 3 2+ 2+ (a) 2 1 2+ 1+ (a) 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
102
MB90630A Series
Table 21 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC rel BBC BBS BBS rel BBS dir:bp, rel addr16:bp, io:bp, rel dir:bp, rel addr16:bp, io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 RG 0 0 0 Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LA HH Z Z Z - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - -
0 2x (b) bit (dir:bp) b (A) 0 2x (b) bit (addr16:bp) b (A) 0 2x (b) bit (io:bp) b (A) 0 2x (b) bit (dir:bp) b 1 0 2x (b) bit (addr16:bp) b 1 0 2x (b) bit (io:bp) b 1 0 2x (b) bit (dir:bp) b 0 0 2x (b) bit (addr16:bp) b 0 0 2x (b) bit (io:bp) b 0 0 0 0 0 0 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
0 2x (b) Branch when (addr16:bp) b = 1, - bit = 1 0 - *5 Wait until (io:bp) b = 1 0 - *5 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
103
MB90630A Series
Table 22 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 R G 0 0 0 0 0 0 B 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension LA HH - - X - Z - - * - X - Z I - - - - - - S - - - - - - T - - - - - - N - - * * R R Z - - * * * * V - - - - - - C RM W - - - - - - - - - - - -
Table 23 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ *2 *2 *1 *1 R GB *5 *5 *5 *5
String Instructions [10 Instructions] Operation LA HH - - - - - - - - - - I - - - - - S - - - - - T - - - - - N - - * * * Z - - * * * V - - * * - C RM W - - * * - - - - - -
2 6m +6 *5
*3 Byte transfer @AH+ @AL+, counter *3 = RW0 Byte transfer @AH- @AL-, counter *4 = RW0 *4 Byte retrieval (@AH+) - AL, counter = *3 RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0
MOVSW/ MOVSWI MOVSWD SCWEQ/ SCWEQI SCWEQD FILSW/FILSWI
2 2 2 2
*2 *2 *1 *1
*8 *8 *8 *8
2 6m +6 *8
*6 Word transfer @AH+ @AL+, counter *6 = RW0 Word transfer @AH- @AL-, counter *7 = RW0 *7 Word retrieval (@AH+) - AL, counter = *6 RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - * * *
- - * * *
- - * * -
- - * * -
- - - - -
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 104
MB90630A Series
s ORDERING INFORMATION
Model MB90632APFV MB90634APFV MB90P634APFV MB90632APF MB90634APF MB90P634APF Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) MB90P634A supports ES alone. Remarks
105
MB90630A Series
s PACKAGE DIMENSIONS
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mounting height) (Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007 -.001
+0.08 +.003
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
100-pin Plastic QFP (FPT-100P-M06)
80 81
23.900.40(.941.016) 20.000.20(.787.008)
51 50
3.35(.132)MAX (Mounting height) (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
106
MB90630A Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0004 (c) FUJITSU LIMITED Printed in Japan

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